Patterned silicide structures and methods of manufacture

Patent metadata

Field	Value
Publication number	US-11107979-B2
Application number	US-201816236275-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 28, 2018
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

First claim

What is claimed is:

1. A method of forming an interconnect in an Integrated Circuit (IC) comprising:
forming a first set of silicide regions in portions of a substrate;
selectively etching the substrate to form a plurality of trenches into the substrate along-side the first set of silicide regions and extending below the first set of silicide regions;
filling the trenches with a first dielectric layer:
forming a second dielectric layer, a conductive layer and a third dielectric layer over the first set of silicide regions and the first dielectric layer filling the trenches;
selectively etching the second dielectric layer, the conductive layer and the third dielectric layer to form a plurality of openings substantially aligned to the first set of silicide regions, wherein sets of the plurality of openings extend to corresponding ones of the first set of silicide regions;
forming a fourth dielectric layer on exposed surfaces of the one or more conductive layers in the plurality of openings; and
forming an semiconductor material with various degree of crystallinity in the plurality of openings after formation of the fourth dielectric layer.

2. The method of claim 1 , further comprising forming a plurality of Magnetic Tunnel Junction (MTJ) cells respectively coupled to the semiconductor material with various degree of crystallinity in the plurality of opening.

3. The method of claim 1 , wherein the first set of silicide regions are formed proximate a surface of the substrate.

4. The method of claim 1 , wherein the first set of silicide regions are formed buried in the substrate.

5. The method of claim 1 , further comprising:
forming a first doped region in the semiconductor material with various degree of crystallinity proximate the first set of silicide regions, wherein the first doped region has a first doping concentration of a first type of dopant;
forming a second doped region in the semiconductor material with various degree of crystallinity, wherein the second dope region has a second doping concentration of the first type of dopant; and
wherein the semiconductor material with various degree of crystallinity between the first and second doped regions has a third doping concentration of a second type of dopant.

6. A method of forming a Magnetic Tunnel Junction (MTJ) memory array comprising:
forming a mask on a semiconductor substrate, wherein the mask includes openings with a large length to width ratio;
forming a first set of silicide regions in portions of the semiconductor substrate exposed by the openings in the mask;
selectively etching the semiconductor substrate to form a set of trenches into the semiconductor substrate self-aligned to the first set of silicide regions and extending below the first set of silicide regions;
depositing a nitride layer on the walls of the trenches;
depositing a first dielectric layer in the trenches after formation of the nitride layer:
depositing a second dielectric layer over the first set of silicide regions and the first dielectric layer in the trenches;
depositing a first conductive layer over the second dielectric layer;
depositing a third dielectric layer over the first conductive layer;
selectively etching through the third dielectric layer, the first conductive layer and the second dielectric layer to form a plurality of holes substantially aligned to the first set of silicide regions;
depositing a fourth dielectric layer on the walls of the plurality of holes; and
epitaxially depositing a semiconductor in the plurality of holes after formation of the fourth dielectric layer on the walls of the plurality of holes.

7. The method of claim 6 , wherein forming the first set of silicide regions comprises:
implanting one or more metals in the semiconductor substrate exposed by the mask; and
thermally annealing the semiconductor substrate to cause the implanted one or metals to form the first set of silicide regions in the semiconductor substrate.

8. The method of claim 7 , wherein:
the one or more metals are implanted proximate a surface of the semiconductor substrate; and
the first set of silicide regions are formed proximate a surface of the semiconductor substrate.

9. The method of claim 7 , wherein:
the one or more metals are implanted below a surface of the semiconductor substrate; and
the first set of silicide regions are formed buried in the semiconductor substrate.

10. The method of claim 6 , wherein the first set of silicide regions comprise at least a portion of substantially parallel source lines arranged along columns of an array.

11. The method of claim 6 , further comprising:
forming a sacrificial semiconductor material with various degree of crystallinity layer on the fourth dielectric layer on the walls of the plurality of holes; and
anisotropy etching the sacrificial semiconductor material with various degree of crystallinity layer to open up epitaxial growth locations on the first set of silicide regions before formation of the epitaxial semiconductor in the plurality of holes.

12. The method of claim 6 , further comprising:
forming drain regions of selectors having a first concentration of a first type of dopant in the epitaxial deposited semiconductor proximate the set of silicide regions;
forming source regions of the selectors having a second concentration of the first type of dopant in the epitaxial deposited semiconductor; and
forming body regions of the selectors having a first concentration of a second type of dopant in the epitaxial deposited semiconductor between the source regions and drain regions.

13. The method of claim 6 , further comprising:
forming a second set of silicide regions on a surface of the epitaxial semiconductor;
depositing a reference magnetic layer coupled to the second set of silicide regions;
depositing a tunneling barrier layer on the reference magnetic layer; and
depositing a free magnetic layer on the tunneling barrier layer; and
etching through the free magnetic layer, the tunneling barrier layer and the reference magnetic layer to form a plurality of Magnetic Tunnel Junction (MTJ) cell pillars coupled to the epitaxial semiconductor in corresponding ones of the plurality of holes by corresponding one of the second set of silicide regions.

14. The method of claim 13 , further comprising:
depositing a fifth dielectric layer over the plurality of MTJ cell pillars;
selective etching a plurality of bit line vias in the fifth dielectric layer aligned with the MTJ cell pillars;
depositing a second conductive layer in the plurality of bit line vias and over the fifth dielectric layer; and
selectively etching the second conductive layer to form a plurality of bit lines arranged along columns of an array and coupled to the MTJ cell pillars through the bit line vias.

15. A method of forming a Magnetic Tunnel Junction (MTJ) memory array comprising:
forming a first silicide region in a semiconductor substrate;
forming a mask on a semiconductor substrate, wherein the mask includes openings with a large length to width ratio;
selectively etching the semiconductor substrate exposed by the mask to form a set of trenches into the semiconductor substrate and a first set of silicide regions disposed between the trenches, wherein the trenches extend below the first set of silicide regions;
depositing a nitride layer on the walls of the trenches;
depositing a first dielectric layer in the trenches after formation of the nitride layer:
depositing a second dielectric layer over the first set of silicide regions and the first dielectric layer in the trenches;
depositing a f

Assignees

• Spin Memory Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Gajek Marcin
• Tzoufras Michail
• Bozdag Kadriye Deniz
• Ryan Eric
• Araki Satoru
• Walker Andy

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title