Shift register unit, driving method thereof, scan driving circuit and display panel

Patent metadata

Field	Value
Publication number	US-11106296-B2
Application number	US-201716078061-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Apr 24, 2017
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

A shift register unit includes an input circuit, a first control circuit, a second control circuit, a third control circuit, a first output circuit, and a second output circuit. The first and second output circuits selectively transfer a first reference voltage from a first reference voltage terminal and a third reference voltage from a third reference voltage terminal to an output terminal of the shift register unit. This allows the shift register unit to output a desired output signal in an easy manner.

First claim

What is claimed is:

1. A shift register unit comprising:
an input circuit configured to transfer an input signal from an input terminal to a first node in response to a first clock signal from a first clock signal terminal being active;
a first control circuit configured to transfer a first reference voltage from a first reference voltage terminal to the first node in response to a second node being at an active potential and a second clock signal from a second clock signal terminal being active, and to transfer the first clock signal from the first clock signal terminal to the second node in response to the first node being at an active potential;
a second control circuit configured to transfer a second reference voltage from a second reference voltage terminal to the second node in response to the first clock signal from the first clock signal terminal being active, and to transfer the second clock signal from the second clock signal terminal to a third node in response to the second node being at an active potential;
a third control circuit configured to bring the third node into conduction with a fourth node in response to the second clock signal from the second clock signal terminal being active, and to transfer the first reference voltage from the first reference voltage terminal to the fourth node in response to the first node being at an active potential;
a first output circuit configured to transfer the first reference voltage from the first reference voltage terminal to an output terminal in response to the fourth node being at an active potential; and
a second output circuit configured to transfer a third reference voltage from a third reference voltage terminal to the output terminal in response to the first node being at an active potential.

2. The shift register unit of claim 1 , wherein the input circuit comprises a first transistor having a gate connected to the first clock signal terminal, a first electrode of the first transistor connected to the input terminal, and a second electrode of the first transistor connected to the first node.

3. The shift register unit of claim 1 , wherein the first control circuit comprises:
a second transistor having a gate connected to the first node, a first electrode of the second transistor connected to the first clock signal terminal, and a second electrode of the second transistor connected to the second node;
a third transistor having a gate connected to the second node, a first electrode of the third transistor connected to the first reference voltage terminal, and a second electrode of the third transistor; and
a fourth transistor having a gate connected to the second clock signal terminal, a first electrode of the fourth transistor connected to the second electrode of the third transistor, and a second electrode of the fourth transistor connected to the first node.

4. The shift register unit of claim 1 , wherein the second control circuit comprises:
a fifth transistor having a gate connected to the first clock signal terminal, a first electrode of the fifth transistor connected to the second reference voltage terminal, and a second electrode of the fifth transistor connected to the second node;
a sixth transistor having a gate connected to the second node, a first electrode of the sixth transistor connected to the second clock signal terminal, and a second electrode of the sixth transistor connected to the third node; and
a first capacitor connected between the second node and the third node.

5. The shift register unit of claim 1 , wherein the third control circuit comprises:
a seventh transistor having a gate connected to the second clock signal terminal, a first electrode of the seventh transistor connected to the third node, and a second electrode of the seventh transistor connected to the fourth node; and
an eighth transistor having a gate connected to the first node, a first electrode of the eighth transistor connected to the first reference voltage terminal, and a second electrode of the eighth transistor connected to the fourth node.

6. The shift register unit of claim 1 , wherein the first output circuit comprises:
a ninth transistor having a gate connected to the fourth node, a first electrode of the ninth transistor connected to the first reference voltage terminal, and a second electrode of the ninth transistor connected to the output terminal of the shift register unit; and
a second capacitor connected between the fourth node and the first reference voltage terminal.

7. The shift register unit of claim 1 , wherein the second output circuit comprises:
a tenth transistor having a gate connected to the first node, a first electrode of the tenth transistor connected to the third reference voltage terminal, and a second electrode of the tenth transistor connected to the output terminal of the shift register unit; and
a third capacitor connected between the first node and the second clock signal terminal.

8. The shift register unit of claim 1 , wherein the third reference voltage terminal and the second reference voltage terminal are a same signal terminal.

9. A scan driving circuit comprising a plurality of shift register units as claimed in claim 1 in a cascaded configuration, wherein except for a first one of the plurality of shift register units, the input terminal of each of the plurality of shift registers is connected to the output terminal of an adjacent preceding one of the shift register units.

10. A display panel comprising the scan driving circuit as claimed in claim 9 .

11. The display panel of claim 10 , wherein the display panel is a self-capacitive touch screen configured to alternately operate in a display phase and a touch sensing phase, and wherein the third reference voltage terminal of each of the plurality of shift register units of the scan driving circuit is configured to receive a direct current voltage as the third reference voltage during the display phase and receive a superposition of the direct current voltage and a touch scan signal for touch electrodes of the self-capacitive touch screen during the touch sensing phase.

12. The scan driving circuit of claim 9 , wherein the input circuit comprises a first transistor having a gate connected to the first clock signal terminal, a first electrode connected to the input terminal, and a second electrode connected to the first node.

13. The scan driving circuit of claim 9 , wherein the first control circuit comprises:
a second transistor having a gate connected to the first node, a first electrode of the second transistor connected to the first clock signal terminal, and a second electrode of the second transistor connected to the second node;
a third transistor having a gate connected to the second node, a first electrode of the third transistor connected to the first reference voltage terminal, and a second electrode of the third transistor; and
a fourth transistor having a gate connected to the second clock signal terminal, a first electrode of the fourth transistor connected to the second electrode of the third transistor, and a second electrode of the fourth transistor connected to the first node.

14. The scan driving circuit of claim 9 , wherein the second control circuit comprises:
a fifth transistor having a gate connected to the first clock signal terminal, a first electrode of the fifth transistor connected to the second reference voltage terminal, and a second electrode of the fifth transistor connected to the second node;
a sixth transistor having a gate connected to the second node, a first electrode of the sixth transistor connected to the second clock signal termin

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yang Shengji
• Dong Xue
• Lv Jing
• Chen Xiaochuan
• Liu Dongni
• Wang Lei
• Lu Pengcheng
• Fu Jie
• Yue Han
• Xiao Li

Classifications

• G06F3/0418

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G06F3/04166

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title