Fabrication method of semiconductor package with stacked semiconductor chips

Patent metadata

Field	Value
Publication number	US-11101235-B2
Application number	US-202016742040-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	May 11, 2012
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

First claim

What is claimed is:

1. A fabrication method of a semiconductor package, comprising the steps of:
providing a carrier having a first surface with a plurality of conductive pads and a second surface opposite to the first surface;
disposing a first semiconductor chip on the first surface of the carrier in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;
thinning the first semiconductor chip from the first non-active surface thereof;
forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;
forming in the first through holes a plurality of bumps electrically connected to the first electrode pads, and forming a heat conducting layer on the first non-active surface of the first semiconductor chip, wherein a solder material is formed on and in direct contact with the bumps;
disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element and the bumps; and
forming on the first surface of the carrier an encapsulant that encapsulates the first semiconductor chip and the electronic element.

2. The fabrication method of claim 1 , wherein the first electrode pads are exposed through the first through holes, respectively.

3. The fabrication method of claim 1 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

4. The fabrication method of claim 1 , wherein the bumps are formed through an electroplating process or an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) process, or formed through solder paste print and reflow.

5. The fabrication method of claim 1 , wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

6. The fabrication method of claim 1 , wherein the carrier is a circuit board or a packaging substrate.

7. The fabrication method of claim 1 , wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

8. The fabrication method of claim 1 , further comprising disposing a second semiconductor chip between the first semiconductor chip and the electronic element.

9. The fabrication method of claim 1 , further comprising forming on the first non-active surface of the first semiconductor chip a circuit layer electrically connected to the bumps.

10. The fabrication method of claim 1 , further comprising attaching a heat sink to the encapsulant.

11. The fabrication method of claim 10 , further comprising forming a thermal adhesive between the heat sink and the encapsulant.

12. The fabrication method of claim 1 , further comprising attaching a heat sink to the encapsulant and connecting the heat sink to the heat conducting layer.

13. A fabrication method of a semiconductor package, comprising the steps of:
providing a carrier having a first surface with a plurality of conductive elements and a second surface opposite to the first surface;
disposing a first semiconductor chip on the first surface of the carrier in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive elements, respectively;
thinning the first semiconductor chip from the first non-active surface thereof;
forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;
forming in the first through holes a plurality of first bumps made of solder electrically connected to the first electrode pads;
disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element to the first bumps; and
forming on the first surface of the carrier an encapsulant that encapsulates the first semiconductor chip and the electronic element.

14. The fabrication method of claim 13 , wherein the first electrode pads are exposed through the first through holes, respectively.

15. The fabrication method of claim 13 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

16. The fabrication method of claim 13 , wherein the first bumps are formed through an electroplating process or an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) process, or formed through solder paste print and reflow.

17. The fabrication method of claim 13 , wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

18. The fabrication method of claim 13 , wherein the carrier is a silicon wafer, an aluminum coated wafer or a glass sheet.

19. The fabrication method of claim 13 , wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

20. The fabrication method of claim 13 , further comprising disposing a second semiconductor chip between the first semiconductor chip and the electronic element.

21. The fabrication method of claim 13 , further comprising forming on the first non-active surface of the first semiconductor chip a circuit layer electrically connected to the first bumps.

22. The fabrication method of claim 13 , further comprising attaching a heat sink to the encapsulant.

23. The fabrication method of claim 22 , further comprising forming a thermal adhesive between the heat sink and the encapsulant.

24. The fabrication method of claim 13 , further comprising forming a heat conducting layer on the first non-active surface of the first semiconductor chip.

25. A fabrication method of a semiconductor package, comprising the steps of:
providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from a top surface thereof;
disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively, and a plurality of first bumps made of solder are formed in the first semiconductor chip and electrically connected to the first electrode pads;
thinning the first semiconductor chip from the first non-active surface thereof so as to expose the first bumps;
disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element and the first bumps; and
forming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.

26. The fabrication method of claim 25 , wherein the build-up structure has a plurality of bonding pads in contact with the first surface of the carrier, and the method further comprises removing the carrier to expose the bonding pads.

27. The fabrication method of claim 25

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title