Wrapped signal shielding in a wafer fanout package

Patent metadata

Field	Value
Publication number	US-11101224-B2
Application number	US-201815877283-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Jun 8, 2017
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a die that includes a plurality of bump sites; and
a substrate connected to the die at the plurality of bump sites, the substrate including at least one layer that implements both one or more signal traces and a plurality of shield traces, wherein each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias, each of the plurality of slot vias positioned along a length of each shield trace in the substrate and one or more of the signal traces is interposed between at least two of the plurality of shield traces in the at least one layer, each slot via comprising an elongated hole axially parallel to the length of the shield trace.

2. The IC package of claim 1 , wherein each slot via comprises an array of microvias.

3. The IC package of claim 2 , wherein each microvia in the array of microvias comprises a hole formed in a dielectric material of the substrate and plated or filled conductive material in the hole.

4. The IC package of claim 3 , wherein the hole is formed using a laser drilling technique.

5. The IC package of claim 1 , wherein each slot via is formed in a dielectric material of the substrate and is plated or filled with conductive material.

6. The IC package of claim 5 , wherein the elongated hole or a trench is formed using at least one of laser etching, laser chemical etching, plasma etching, metal assisted chemical etching, or a lithography defined polyimide or PBO (Polybenzoazole) pattern.

7. The IC package of claim 1 , wherein each shield trace in the plurality of shield traces includes an interconnect and an extension in the substrate such that a height of the shield trace is larger than a height of a corresponding signal trace.

8. The IC package of claim 7 , wherein the interconnect is wider than the extension.

9. The IC package of claim 1 , wherein each shield trace in the plurality of shield traces is coupled to a second ground plane by a plurality of additional slot vias.

10. The IC package of claim 1 wherein the length of the shield trace is defined by a first end and a second end, and further including an end via positioned at at least one of the first end or the second end, the plurality of slot vias being formed between the first end and the second end.

11. A system, comprising:
an integrated circuit (IC) package including:
a die that includes a plurality of bump sites; and
a substrate connected to the die at the plurality of bump sites, the substrate including at least one layer that implements one or more signal traces and a plurality of shield traces, wherein each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias, each of the plurality of slot vias positioned along a length of each shield trace in the substrate, each slot via comprising an elongated hole axially parallel to the length of the shield trace, and one or more of the signal traces is interposed between ones of the plurality of shield traces in the at least one layer.

12. The system of claim 11 , wherein each slot via comprises an array of microvias.

13. The system of claim 12 , wherein each microvia in the array of microvias comprises a hole in a dielectric material of the substrate that is plated or filled with a conductive material.

14. The system of claim 11 , wherein each slot via is created by forming an elongated hole or a trench open in a dielectric material of the substrate that is plated or filled with conductive material in the elongated hole or trench.

15. The system of claim 11 , wherein each shield trace in the plurality of shield traces includes an interconnect and an extension in the substrate such that a height of the shield trace is larger than a height of a corresponding signal trace.

16. The system of claim 11 , wherein each shield trace in the plurality of shield traces is coupled to a second ground plane by a plurality of additional slot vias.

17. The system of claim 11 , the system further including a printed circuit board, wherein the IC package is mounted to the printed circuit board.

18. An integrated circuit (IC) package, comprising:
a die that includes a plurality of bump sites; and
a substrate connected to the die at the plurality of bump sites, the substrate including at least one layer that implements both one or more signal traces and a plurality of shield traces, wherein each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias, and one or more of the signal traces is interposed between at least two of the plurality of shield traces in the at least one layer, each slot via comprising an elongated hole axially parallel to a length of the shield trace, wherein the length of the shield trace is defined by a first end and a second end, and further including an end via positioned at at least one of the first end or the second end, the plurality of slot vias formed between the first end and the second end.

19. The package of claim 18 , wherein each slot via comprises an array of microvias.

20. The system of claim 19 , wherein each microvia in the array of microvias comprises a hole in a dielectric material of the substrate that is plated or filled with a conductive material.

Assignees

• Futurewei Technologies Inc

Inventors

• Gu Shiqun
• Liu Tiejun
• Chen Zhao

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title