Regional adjustment of render rate

Patent metadata

Field	Value
Publication number	US-11099800-B2
Application number	US-202016881262-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	Apr 17, 2017
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

First claim

What is claimed:

1. A non-transitory storage medium comprising instructions that when executed cause a graphics processor comprising a plurality of graphics processing cores to perform a method comprising:
identifying a first region of a display that a user is looking at for an amount of time that exceeds a threshold;
in response determining that the user is looking at the first region for the amount of time that exceeds the threshold, anti-aliasing the first region with multi-sampled anti-aliasing, including rendering the first region at a first render rate; and
anti-aliasing a second region of the display that the user is not looking at with temporal anti-aliasing, including rendering the second region at a second render rate less than the first render rate.

2. The non-transitory storage medium of claim 1 , further comprising instructions that when executed cause the graphics processor to receive three color planes in the first region.

3. The non-transitory storage medium of claim 1 , further comprising instructions that when executed cause the graphics processor to adjust the first render rate for the first region based on gaze time of the user.

4. The non-transitory storage medium of claim 1 , further comprising instructions that when executed cause the graphics processor to increase the first render rate and reduce the second render rate.

5. The non-transitory storage medium of claim 1 , further comprising instructions that when executed cause the graphics processor to increase the first render rate and reduce the second render rate based on prediction information.

6. The non-transitory storage medium of claim 1 , further comprising instructions that when executed cause the graphics processor to control the first render rate to be twice the second render rate.

7. A graphics processing unit, comprising:
an interface to couple the graphics processing unit to a processor,
a plurality of texture units,
a shared memory coupled to the plurality of texture units,
a plurality of register files coupled to the shared memory,
a plurality of load/store units coupled to the shared memory,
a plurality of graphics processing cores coupled to the plurality of register files, and
a non-transitory storage medium comprising instructions that when executed cause at least some of the plurality of graphics processing cores to:
identify a first region of a display that a user is looking at for an amount of time that exceeds a threshold;
in response to a determination that the user is looking at the first region for the amount of time that exceeds the threshold, anti-alias the first region with multi-sampled anti-aliasing, including to render the first region at a first render rate; and
anti-alias a second region of the display that the user is not looking at with temporal anti-aliasing, including to render the second region at a second render rate less than the first render rate.

8. The graphics processing unit of claim 7 , further comprising scheduler logic to schedule groups of instructions.

9. The graphics processing unit of claim 8 , further comprising a plurality of arithmetic logic units coupled to the plurality of register files, wherein the plurality of arithmetic logic units are to perform operations on integer data types.

10. The graphics processing unit of claim 9 , further comprising at least one memory unit.

11. The graphics processing unit of claim 10 , wherein the memory unit comprises a load and store unit.

12. The graphics processing unit of claim 7 , wherein the non-transitory storage medium further comprises instructions that when executed cause the at least some of the plurality of graphics processing cores to receive three color planes in the first region.

13. The graphics processing unit of claim 7 , wherein the non-transitory storage medium further comprises instructions that when executed cause the at least some of the plurality of graphics processing cores to adjust the first render rate for the first region based on gaze time of the user.

14. The graphics processing unit of claim 7 , wherein the non-transitory storage medium further comprises instructions that when executed cause the at least some of the plurality of graphics processing cores to increase the first render rate and reduce the second render rate.

15. The graphics processing unit of claim 7 , wherein the non-transitory storage medium further comprises instructions that when executed cause the at least some of the plurality of graphics processing cores to increase the first render rate and reduce the second render rate based on prediction information.

16. The graphics processing unit of claim 7 , wherein the non-transitory storage medium further comprises instructions that when executed cause the at least some of the plurality of graphics processing cores to control the first render rate to be twice the second render rate.

17. A graphics processor, comprising:
a register file to store information;
a plurality of arithmetic logic units coupled to the register file;
a plurality of texture units coupled to the register file; and
a non-transitory storage medium comprising instructions that when executed cause the graphics processor to:
identify a first region of a display that a user is looking at for an amount of time that exceeds a threshold;
in response to a determination that the user is looking at the first region for the amount of time that exceeds the threshold, anti-alias the first region with multi-sampled anti-aliasing, including to render the first region at a first render rate; and
anti-alias a second region of the display that the user is not looking at with temporal anti-aliasing, including to render the second region at a second render rate less than the first render rate.

18. The graphics processor of claim 17 , further comprising scheduler logic to schedule groups of instructions.

19. The graphics processor of claim 18 , further comprising a plurality of arithmetic logic units coupled to the register file, wherein the plurality of arithmetic logic units are to perform operations on integer data types.

20. The graphics processor of claim 17 , wherein the non-transitory storage medium further comprises instructions that when executed cause the graphics processor to adjust the first render rate for the first region based on gaze time of the user.

Assignees

• Intel Corp

Inventors

• Asperheim Eric J
• Maiyuran Subramaniam M
• Veernapu Kiran C
• Jahagirdar Sanjeev S
• Vembu Balaji
• Burke Devan
• Laws Philip R
• Sinha Kamal
• Appu Abhishek R
• Ould-Ahmed-Vall Elmoustapha
• Doyle Peter L
• Ray Joydeep
• Schluessler Travis T
• Feit John H
• Kaburlasos Nikos
• Kwiatkowski Jacek
• Koker Altug

Classifications

• G09G5/001

  Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor · CPC title

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title

• G06F3/013

  Eye tracking input arrangements (G06F3/015 takes precedence) · CPC title

• G09G2354/00

  Aspects of interface with display user · CPC title

• G09G2360/121

  using a cache memory · CPC title