Printed circuit board shielding and power distribution via edge plating

Patent metadata

Field	Value
Publication number	US-11096277-B2
Application number	US-201916568908-A
Country	US
Kind code	B2
Filing date	Sep 12, 2019
Priority date	Sep 12, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A circuit board and method of manufacture therefor utilize voltage domain edge plating disposed on at least a portion of one or more edges of a circuit board to electrically couple voltage domain conductive shapes disposed in different conductive layers of the circuit board. By doing so, interconnection of multiple voltage domain conductive shapes in different conductive layers may be facilitated with improved power integrity, while also providing EMI shielding along the edge of the circuit board.

First claim

What is claimed is:

1. A circuit board, comprising:
a stack including a plurality of conductive layers separated from one another by a plurality of dielectric layers, the stack further including a plurality of edges defining at least a portion of a perimeter of the stack;
a voltage domain including first and second voltage domain conductive shapes disposed on different conductive layers among the plurality of conductive layers;
edge plating disposed on at least a portion of one of the plurality of edges and electrically coupling the first and second voltage domain conductive shapes to one another; and
at least one decoupling capacitor disposed on a top or bottom surface of the stack proximate one or more of the plurality of edges and electrically coupled between the edge plating and a ground reference through an associated via, the ground reference disposed in a conductive layer of the plurality of conductive layers.

2. The circuit board of claim 1 , wherein the edge plating is directly coupled to each of the first and second voltage domain conductive shapes.

3. The circuit board of claim 1 , wherein the edge plating is coupled to at least one of the first and second voltage domain conductive shapes through a conductive via extending through at least a portion of the stack.

4. The circuit board of claim 1 , wherein the edge plating is electroplated edge plating.

5. The circuit board of claim 1 , wherein the at least one decoupling capacitor includes a plurality of decoupling capacitors disposed at regular intervals.

6. The circuit board of claim 1 , wherein the edge plating is first edge plating disposed on a first portion of a first edge among the plurality of edges, and wherein the circuit board further comprises second edge plating disposed on a second portion of the first edge.

7. The circuit board of claim 6 , further comprising a ground reference including first and second ground conductive shapes disposed on different conductive layers among the plurality of conductive layers, wherein the second edge plating electrically couples the first and second ground conductive shapes to one another.

8. The circuit board of claim 6 , wherein the voltage domain is a first voltage domain, wherein the circuit board further comprises a second voltage domain including third and fourth voltage domain conductive shapes disposed on different conductive layers among the plurality of conductive layers, wherein the second edge plating electrically couples the third and fourth voltage domain conductive shapes to one another.

9. The circuit board of claim 6 , wherein the first and second edge plating are disposed at different lateral positions along the first edge.

10. The circuit board of claim 6 , wherein the first edge has a thickness, and wherein the first edge plating spans only a first portion of the thickness of the first edge at least at a first lateral position along the first edge.

11. The circuit board of claim 10 , wherein the second edge plating spans a second portion of the thickness of the first edge at least at the first lateral position along the first edge.

12. The circuit board of claim 6 , wherein the first and second edge plating are formed by etching conductive material electroplated onto the first edge.

13. The circuit board of claim 1 , further comprising a protective insulating coating overlying the edge plating.

Assignees

• IBM

Inventors

• Del Rosal Edni
• Yuksel Anil
• Green David

Classifications

• H05K2201/09618

  Via fence, i.e. one-dimensional array of vias · CPC title

• H05K1/0218 Primary

  by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence) · CPC title

• H05K2201/09354

  Ground conductor along edge of main surface · CPC title

• H05K1/0298 Primary

  Multilayer circuits · CPC title

• H05K2201/0919

  Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes · CPC title