Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11095300-B2
Application number	US-202016904604-A
Country	US
Kind code	B2
Filing date	Jun 18, 2020
Priority date	Dec 11, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

First claim

What is claimed is:

1. A comparator circuit, comprising:
a first transistor having a gate, a drain and a source wherein the first transistor is configured to receive a first input;
a second transistor having a gate, a drain and a source wherein the second transistor is configured to receive a second input;
a third transistor having a gate, a drain and a source wherein the drain of the third transistor is directly coupled to the source of the first transistor and to the source of the second transistor, and the gate of the third transistor is connected to a fixed voltage;
a fourth transistor having a gate, a drain and a source wherein the source of the fourth transistor is coupled to the fixed voltage;
a fifth transistor having a gate, a drain and a source wherein the gate of the fifth transistor is coupled to the drain of the fourth transistor at a first node, the gate of the fourth transistor is coupled to a the drain of the fifth transistor at a second node and the source of the fifth transistor is coupled to the fixed voltage; and
a sixth transistor having a gate, a drain and a source wherein the drain of the sixth transistor is coupled to the drain of the fourth transistor, the source of the sixth transistor is coupled to the drain of the first transistor and the gate of the sixth transistor is coupled to the fixed voltage; and
a seventh transistor having a gate, a drain and a source wherein the drain of the seventh transistor is coupled to the drain of the fifth transistor, the source of the seventh transistor is coupled to the drain of the second transistor and the gate of the seventh transistor is coupled to the fixed voltage.

2. The comparator circuit of claim 1 , wherein the first, second, sixth and seventh transistors comprise p-type metal oxide semiconductor field effect transistors.

3. The comparator circuit of claim 1 , further comprising:
an eighth transistor having a gate, drain and source wherein the drain is coupled to the first node, wherein the gate of the eighth transistor is coupled to the second node; and
a ninth transistor having a gate, drain and source wherein the drain is coupled to the second node, wherein the gate of the ninth transistor is coupled to the first node.

4. The comparator circuit of claim 3 , further comprising a tenth transistor having a gate, drain and source wherein the drain is coupled to a the source of the eighth transistor and to the source of the ninth transistor, and the gate of the tenth transistor is coupled to the fixed voltage.

5. The comparator circuit of claim 1 , wherein the fourth and fifth transistors comprise n-type metal oxide semiconductor field effect transistors and the eighth and ninth transistors comprise p-type metal oxide semiconductor field effect transistors.

6. A system comprising:
an analog-to-digital converter (ADC), the ADC comprising;
a first transistor having a gate, a drain and a source wherein the first transistor is configured to receive a first input;

a second transistor having a gate, a drain and a source wherein the second transistor is configured to receive a second input;
a third transistor having a gate, a drain and a source wherein the drain of the third transistor is directly coupled to the source of the first transistor and to the source of the second transistor, and the gate of the third transistor is connected to a fixed voltage;
a fourth transistor having a gate, a drain and a source wherein the source of the fourth transistor is coupled to the fixed voltage;
a fifth transistor having a gate, a drain and a source wherein the gate of the fifth transistor is coupled to the drain of the fourth transistor at a first node, the gate of the fourth transistor is coupled to the drain of the fifth transistor at a second node and the source of the fifth transistor is coupled to the fixed voltage; and
a sixth transistor having a gate, a drain and a source wherein the drain of the sixth transistor is coupled to the drain of the fourth transistor, the source of the sixth transistor is coupled to the drain of the first transistor and the gate of the sixth transistor is coupled to the fixed voltage; and
a seventh transistor having a gate, a drain and a source wherein the drain of the seventh transistor is coupled to the drain of the fifth transistor, the source of the seventh transistor is coupled to the drain of the second transistor and the gate of the seventh transistor is coupled to the fixed voltage.

7. The system of claim 6 , wherein the first, second, sixth and seventh transistors comprise p-type metal oxide semiconductor field effect transistors.

8. The system of claim 6 , further comprising:
an eighth transistor having a gate, drain and source wherein the drain is coupled to the first node, wherein the gate of the eighth transistor is coupled to the second node; and
a ninth transistor having a gate, drain and source wherein the drain is coupled to the second node, wherein the gate of the ninth transistor is coupled to the first node.

9. The system of claim 8 , further comprising a tenth transistor having a gate, drain and source wherein the drain is coupled to the source of the eighth transistor and to the source of the ninth transistor, and the gate of the tenth transistor is coupled to the fixed voltage.

10. The system of claim 6 , wherein the fourth and fifth transistors comprise n-type metal oxide semiconductor field effect transistors and the eighth and ninth transistors comprise p-type metal oxide semiconductor field effect transistors.

Assignees

• Texas Instruments Inc

Inventors

• Ghosh Sovan
• Kundu Amal Kumar
• Seetharaman Janakiraman

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/089 Primary

  of temperature variations · CPC title