Level shifter circuit and associated memory device

Patent metadata

Field	Value
Publication number	US-9972394-B2
Application number	US-201715476003-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Aug 30, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.

First claim

What is claimed is:

1. A level shifter circuit comprising:
a first input inverter stage having an input configured to receive an input signal that switches within a first voltage range, wherein the first input inverter stage is designed to operate in the first voltage range;
a first capacitive element coupled between an output of the first input inverter stage and a first holding node;
a latch stage coupled between the first holding node and a second holding node, the second holding node serving as an output terminal configured to supply an output signal that switches within a second voltage range that is higher than the first voltage range, wherein the latch stage is designed to operate in the second voltage range; and
an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor having a current path coupled between the second holding node and a reference terminal set at an initialization voltage, and having a gate configured to receive a reset signal.

2. The circuit according to claim 1 , wherein the second voltage range has a lower-limit voltage and an upper-limit voltage;
wherein the latch stage has biasing reference inputs configured to receive the lower-limit voltage and the upper-limit voltage;
wherein the latch stage is configured to hold voltage values on the first holding node and the second holding node, alternatively equal to the lower-limit voltage or to the upper-limit voltage; and
wherein the latch stage is configured to switch its operating state following upon switching of the input signal.

3. The circuit according to claim 1 , wherein the latch stage comprises:
a first latch inverter having an input coupled to the first holding node and an output coupled to the second holding node; and
a second latch inverter having an input coupled to the output of the first latch inverter and an output coupled to the input of the first latch inverter, wherein the first and second latch inverters are configured to operate in the second voltage range.

4. The circuit according to claim 1 , wherein the latch stage comprises:
a first PMOS transistor having a gate coupled to the second holding node and a current path coupled between a high voltage node and the first holding node, the high voltage node configured to carry a voltage at an upper end of the second voltage range;
a first NMOS transistor having a gate coupled to the second holding node and a current path coupled between the first holding node and a low voltage node, the low voltage node configured to carry a voltage at a lower end of the second voltage range;
a second PMOS transistor having a gate coupled to the first holding node and a current path coupled between the high voltage node in the second holding node; and
a second NMOS transistor having a gate coupled to the first holding node and a current path coupled between the second holding node and the low voltage node.

5. The circuit according to claim 1 , wherein the initialization stage is configured to control initialization of the second holding node at an initialization voltage to define an initial operating state of the latch stage.

6. The circuit according to claim 1 , further comprising:
a second input inverter stage having an input configured to receive a complementary input signal that switches with the first voltage range, the complementary input signal being a complement of the input signal; and
a second capacitive element coupled between an output of the second input inverter stage and the second holding node.

7. The circuit according to claim 1 , wherein the first capacitive element comprises a MOS transistor having current-conduction terminals connected together, to a respective bulk terminal, and further to the first holding node, the MOS transistor also having a gate terminal coupled to the output of the first input inverter stage.

8. The circuit according to claim 1 , further comprising:
a first output buffer having an input coupled to the first holding node; and
a second output buffer having an input coupled to the second holding node, an output of the second output buffer being the complement of an output of the first output buffer.

9. The circuit according to claim 1 , wherein the input signal is configured to switch between a lower value and an upper value of the first voltage range, and the output signal is configured to switch, between an upper-limit voltage and a lower-limit voltage of the second voltage range.

10. A level shifter circuit comprising:
a first input inverter stage having an input configured to receive an input signal that switches within a first voltage range and an output coupled to a first holding node, wherein the first input inverter stage is configured to operate in the first voltage range;
a latch stage coupled between the first holding node and a second holding node, the second holding node serving as an output terminal configured to supply an output signal that switches within a second voltage range that is higher than the first voltage range, wherein the latch stage is configured to operate in the second voltage range;
a second input inverter stage having an input configured to receive a complementary input signal that switches with the first voltage range, the complementary input signal being a complement of the input signal, the second input inverter stage also having an output coupled to the second holding node, wherein the second input inverter stage is configured to operate in the first voltage range; and
an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor having a current path coupled between the second holding node and a reference terminal set at an initialization voltage, and having a gate configured to receive a reset signal.

11. The circuit according to claim 10 , further comprising:
a first capacitive element coupled between the output of the first input inverter stage and the first holding node; and
a second capacitive element coupled between the output of the second input inverter stage and the second holding node.

12. A memory device, comprising:
a memory array including a plurality of memory cells arranged in rows and columns, the memory cells being coupled to respective wordlines and bitlines;
a decoder stage, configured to select and bias the wordlines or the bitlines as a function of address signals, wherein address signals comprise signals that switch within a first voltage range and the wordlines or bitlines are biased at a voltage within a second voltage range that is greater than first voltage range, wherein the decoder stage comprises a plurality of shifter circuits, each level shifter circuit comprising:
a first input inverter stage having an input configured to receive an address signal, wherein the first input inverter stage is configured to operate in the first voltage range;
a first capacitive element coupled between an output of the first input inverter stage and a first holding node;
a latch stage coupled between the first holding node and a second holding node, the second holding node serving as a terminal configured to supply a bias signal for use with a respective wordline or bitline, wherein the latch stage is configured to operate in the second voltage range; and

an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor

Assignees

• St Microelectronics Srl

Inventors

• Conte Antonino
• Paolino Carmelo
• Perroni Maurizio Francesco
• Polizzi Salvatore

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title