Phase-locked loop and method for calibrating voltage-controlled oscillator therein

Patent metadata

Field	Value
Publication number	US-11095294-B2
Application number	US-202016909976-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Jun 24, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A phase-locked loop (PLL) and a method for calibrating a VCO therein are provided. The PLL comprises a frequency-phase detector, a charge pump, a loop filter, a VCO, a divider and a calibration circuit. The calibration circuit is used to acquire a frequency of an output signal of the VCO, to calibrate the frequency of the output signal according to an expected frequency, and to acquire frequency control parameters of the VCO at the current signal frequency. The amplitude and gain of the output signal are kept constant according to the amplitude control parameters and gain control parameters. The PLL can meet the demands on frequencies of multiple protocols and can adaptively look up and stabilize the suitable frequency. It solves the issue that the amplitude of the output signal of the VCO is not constant when the PLL operates in a large frequency range.

First claim

We claim:

1. A phase-locked loop comprising:
a frequency-phase detector used to generate pulse modulation signals of different widths according to a phase difference between two input square wave signals;
a charge pump used to output current pulses according to the pulse modulation signals inputted;
a loop filter used to perform low-pass filtering on the current pulses and output a voltage control signal;
a voltage controlled oscillator (VCO) used to control a frequency of an output signal according to the voltage control signal;
a divider used to divide the frequency of the output signal, and input the divided signal to the frequency-phase detector; and
a calibration circuit used to acquire the frequency of the output signal from the VCO, calibrate the frequency according to an expected frequency, acquire frequency control parameters of the VCO at a current signal frequency, acquire amplitude control parameters and gain control parameters according to the frequency control parameters, and keep an amplitude and gain of the output signal of the VCO constant according to the amplitude control parameters and the gain control parameters;
wherein the VCO comprises a core module and the calibration circuit comprises a controller and a counter; an input of the counter is connected to an output of the VCO; an output of the counter is connected to an input of the controller; an output of the controller is connected to a control end of the core module;
the core module comprises a current generation circuit, an inductor, a coarse-tuning capacitor array, a first fine-tuning capacitor array, a second fine-tuning capacitor array, a filter, a buffer and an amplification circuit;
the current generation circuit is connected to the inductor; the inductor, the coarse-tuning capacitor array, the first fine-tuning capacitor array, the second fine-tuning capacitor array and the amplification circuit are connected in parallel; an input of the filter acts as an input of the VCO; an iutput of the filter is connected to the first fine-tuning capacitor array and an output of the filter is connected to the second fine-tuning capacitor array; an output of the buffer acts as the output of the VCO; the controller is connected to control ends of the current generation circuit, the coarse-tuning capacitor array, the first fine-tuning capacitor array, and the second fine-tuning capacitor array respectively;
the counter compares the frequency of the output signal of the core module with the expected frequency, and sends comparison results to the controller;
if the frequency of the output signal from the core module is greater than the expected frequency, the controller adjusts the frequency control parameters output to the coarse tuning capacitor array to decrease the frequency of the output signal from the core module until the frequency of the output signal is the expected frequency; and
if the frequency of the output signal from the core module is less than the expected frequency, the controller adjusts the frequency control parameters output to the coarse tuning capacitor array to increase the frequency of the output signal from the core module until the frequency of the output signal is the expected frequency.

2. The phase-locked loop of claim 1 , wherein the controller is configured to control an output current of the current generation circuit according to the amplitude control parameters to control the amplitude of the output signal of the VCO; and
the controller is further configured to control capacitances of the first fine-tuning capacitor array and the second fine-tuning capacitor array to control the gain of the output signal of the VCO according to the gain control parameters.

3. A phase-locked loop comprising,
a frequency-phase detector used to generate pulse modulation signals of different widths according to a phase difference between two input square wave signals;
a charge pump used to output current pulses according to the pulse modulation signals inputted;
a loop filter used to perform low-pass filtering on the current pulses and output a voltage control signal;
a voltage controlled oscillator (VCO) used to control a frequency of an output signal according to the voltage control signal;
a divider used to divide the frequency of the output signal, and input the divided signal to the frequency-phase detector; and
a calibration circuit used to acquire the frequency of the output signal from the VCO, calibrate the frequency according to an expected frequency, acquire frequency control parameters of the VCO at a current signal frequency, acquire amplitude control parameters and gain control parameters according to the frequency control parameters, and keep an amplitude and gain of the output signal of the VCO constant according to the amplitude control parameters and the gain control parameters;
wherein the VCO comprises a plurality of core modules and the calibration circuit comprises a controller and a counter; an input of the counter is connected to an output of the VCO; an output of the counter is connected to an input of the controller, and an output of the controller is connected to a control end of each core module;
the core modules each comprises a current generation circuit, an inductor, a coarse-tuning capacitor array, a first fine-tuning capacitor array, a second fine-tuning capacitor array, a filter, a buffer, and an amplification circuit;
the current generation circuit is connected to the inductor; the inductor, the coarse-tuning capacitor array, the first fine-tuning capacitor array, the second fine-tuning capacitor array and the amplifier circuit are connected in parallel; an input of the filter acts as an input of the VCO; an input of the filter is connected to the first fine-tuning capacitor array and an output of the filter is connected to the second fine-tuning capacitor array; an output of the buffer is the output of the VCO, and the controller is connected to control ends of the current generation circuit, the coarse-tuning capacitor array, the first fine-tuning capacitor array and the second fine-tuning capacitor array in each core module;
the counter acquires the frequency of the output signal of a first core module in the VCO, and compares the frequency of the output signal of the first core module with the expected frequency;
if the frequency of the output signal is different to the expected frequency, the controller adjusts the frequency control parameters output to the coarse-tuning capacitor array in the first core module to adjust the frequency of the output signal of the first core module; and
if all frequencies of the output signals of the first core module are different to the expected frequency, the controller sequentially scans the frequencies of the output signals of the remaining core modules until the frequency of the output signal is the expected frequency.

Assignees

• Gowin Semiconductor Corp

Inventors

• Wu Qiming
• Lin Xiaozhi
• Zhou Qiang
• Wang Yunfeng

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0895 Primary

  Details of the current generators (H03L7/0893 takes precedence) · CPC title