Equalizer and transmitter including the same

Patent metadata

Field	Value
Publication number	US-11095271-B2
Application number	US-201816224850-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Jun 11, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

First claim

What is claimed is:

1. An integrated circuit for generating an equalized signal from serial data according to a channel, the integrated circuit comprising:
a shift register configured to extract a symbol sequence from the serial data;
a data storage configured to store values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence;
a lookup table configured to output the equalized digital signal of a value corresponding to the symbol sequence;
a digital-to-analog converter configured to convert the equalized digital signal into the equalized signal; and
a controller configured to refresh the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal, wherein:
the data storage stores values of the equalized digital signal grouped into a plurality of data sets corresponding to a plurality of filter coefficient sequences, and
the controller is further configured to load one of the plurality of data sets into the lookup table based on the control signal.

2. The integrated circuit of claim 1 , further comprising:
an offset generator configured to provide an offset of the equalized digital signal corresponding to a variation of a filter coefficient; and
a calculator configured to perform an addition or subtraction on at least two of: (1) the values stored in the data storage, (2) the values included in the lookup table, and (3) the offset, wherein
the controller is further configured to provide the variation of the filter coefficient to the offset generator based on the control signal and loads an output value of the calculator into the lookup table.

3. The integrated circuit of claim 2 , wherein the offset generator comprises a step size table configured to output a step size corresponding to a pair of a filter coefficient and a symbol.

4. The integrated circuit of claim 3 , wherein the offset generator comprises:
a counter configured to generate a count value which is increased, decreased, or maintained according to the variation of the filter coefficient; and
a multiplier configured to output the offset by selectively changing a sign of the step size according to the variation of the filter coefficient.

5. The integrated circuit of claim 3 , wherein the controller is further configured to refresh the step size table based on the control signal.

6. The integrated circuit of claim 3 , wherein the offset generator comprises a counter configured to output a count value that increases or decreases according to the variation of the filter coefficient.

7. The integrated circuit of claim 6 , wherein the controller is further configured to repeat refreshing of the lookup table until the count value becomes zero if the variation of the filter coefficient corresponds to a reset of the filter coefficient.

8. The integrated circuit of claim 2 , wherein the controller is further configured to perform clock gating of at least one of the data storage, the offset generator, and the calculator after refreshing the lookup table.

9. The integrated circuit of claim 1 , wherein the data storage is rewritable and configured to store values of the equalized digital signal according to an externally received signal.

10. The integrated circuit of claim 1 , wherein the symbol sequence includes 2-bit symbols.

11. A transmitter for transmitting input data through a channel, the transmitter comprising:
a serializer configured to generate serial data from the input data;
an equalizer comprising a finite impulse response (FIR) filter block configured to use a lookup table that outputs a digital signal corresponding to a symbol sequence extracted from the serial data, and a digital-to-analog converter configured to output an equalized signal by converting the digital signal; and
a driver configured to amplify the equalized signal, wherein:
the FIR filter block configured to refresh the lookup table based on channel information received through the channel, and
the FIR filter block is further configured to refresh the lookup table by adding an offset of the digital signal corresponding to a variation of a filter coefficient.

12. The transmitter of claim 11 , wherein the FIR filter block further comprises a data storage for storing values of the digital signal corresponding to potential symbol sequences and is further configured to refresh the lookup table based on at least one of the values stored in the data storage and values included in the lookup table.

13. The transmitter of claim 12 , wherein:
the data storage stores values of the digital signal grouped into a plurality of data sets corresponding to a plurality of filter coefficient sequences, and
the FIR filter block refreshes the lookup table by loading one of the plurality of data sets.

14. The transmitter of claim 11 , wherein the FIR filter block is configured to adjust previously-applied offsets if the variation of the filter coefficient corresponds to a reset of the filter coefficient.

15. A method for transmitting serial data through a channel, the method comprising:
receiving a control signal generated based on channel information received through the channel;
refreshing a lookup table configured to output an equalized digital signal from a symbol sequence in response to a control signal;
extracting a symbol sequence from the serial data;
providing the symbol sequence to the lookup table; and
converting the equalized digital signal outputted from the lookup table into an analog signal, wherein
the refreshing of the lookup table comprises refreshing the lookup table by adding an offset of the equalized digital signal corresponding to a variation of a filter coefficient.

16. The method of claim 15 , wherein the refreshing of the lookup table comprises loading, from a data storage storing values of the equalized digital signal grouped into a plurality of data sets corresponding to a plurality of filter coefficient sequences, one of the plurality of data sets to the lookup table.

17. The method of claim 16 , further comprising performing clock gating of the data storage after the refreshing of the lookup table is terminated.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Gun-Il
• Lee June-Hee
• Cho Byung-Wook

Classifications

• H03M3/324 Primary

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03H2017/0081

  of FIR filters · CPC title

• H04B1/04

  Circuits · CPC title

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title