Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11094900-B2
Application number	US-201916241997-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Dec 10, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
forming a first metal interconnection in a first inter-metal dielectric (IMD) layer;
performing a treatment process to roughen a top surface of the first metal interconnection without roughening sidewalls of the first metal interconnection for forming protrusions on a top surface of the first metal interconnection, wherein the protrusions expose part of the top surface of the first metal interconnection, each of a bottom surface and a top surface of the protrusions comprise a planar surface, the bottom surface of the protrusions is lower than a top surface of the first IMD layer, and the top surface of the protrusions is higher than a top surface of the first IMD layer; and
forming a carbon nanotube (CNT) junction on the first metal interconnection.

2. The method of claim 1 , wherein the treatment process comprises a NH 3 plasma treatment process.

3. The method of claim 1 , wherein the protrusions and the first metal interconnection comprise same material.

4. The method of claim 1 , wherein the protrusions and the first metal interconnection comprise copper (Cu) or tungsten (W).

5. The method of claim 1 , further comprising
forming a bottom electrode layer on the first IMD layer, the protrusions, and the first metal interconnection;
forming a carbon nanotube (CNT) layer on the bottom electrode layer;
forming a top electrode layer on the CNT layer; and
patterning the top electrode layer, the CNT layer, and the bottom electrode layer to form the CNT junction.

6. The method of claim 5 , further comprising:
forming a cap layer on the first IMD layer and the CNT junction;
forming a second IMD layer on the cap layer; and
forming a second metal interconnection in the second IMD layer and the cap layer to electrically connect the CNT junction.

7. A semiconductor device, comprising:
a first metal interconnection in a first inter-metal dielectric (IMD) layer;
protrusions on the first metal interconnection, wherein the protrusions expose part of a top surface of the first metal interconnection, each of a bottom surface and a top surface of the protrusions comprise a planar surface, the bottom surface of the protrusions is lower than a top surface of the first IMD layer and the top surface of the protrusions is higher than a top surface of the first IMD layer; and
a carbon nanotube (CNT) junction on the first metal interconnection, wherein the CNT junction comprises:
a bottom electrode layer on and directly contacting the protrusions and the first metal interconnection;
a CNT layer on the bottom electrode layer; and
a top electrode layer on the CNT layer.

8. The semiconductor device of claim 7 , further comprising:
a second metal interconnection on the CNT junction;
a cap layer on a sidewall of the CNT junction and on the first IMD layer; and
a second IMD layer on the cap layer and around the second metal interconnection.

9. The semiconductor device of claim 8 , wherein the cap layer comprises:
a first L-shaped portion on one side of the CNT junction; and
a second L-shaped portion on another side of the CNT junction.

10. The semiconductor device of claim 8 , wherein the cap layer contacts the CNT junction and the second metal interconnection directly.

11. The semiconductor device of claim 7 , wherein the protrusions and the first metal interconnection comprise same material.

12. The semiconductor device of claim 7 , wherein the protrusions and the first metal interconnection comprise copper (Cu) or tungsten (W).

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Tsai Bin-Siang
• Yang Chin-Chia

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title