Method of manufacturing memory device

Patent metadata

Field	Value
Publication number	US-11094882-B2
Application number	US-201916360500-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Sep 10, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.

First claim

What is claimed is:

1. A method of manufacturing a memory device, the method comprising:
forming a transistor on a substrate;
forming a lower interlayer insulating layer covering the transistor;
forming a hydrogen supply layer on the lower interlayer insulating layer;
forming a hydrogen blocking layer on the hydrogen supply layer;
annealing the transistor, the lower interlayer insulating layer and the hydrogen supply layer;
forming a memory cell on the hydrogen blocking layer after the annealing of the transistor, the lower interlayer insulating layer and the hydrogen supply layer;
forming an upper inter layer insulating layer surrounding the memory cell; and
further comprising forming at least one intermediate interlayer insulating layer between the hydrogen supply layer and the lower interlayer insulating layer,
wherein the at least one intermediate interlayer insulating layer comprises a first intermediate interlayer insulating layer on the lower interlayer insulation layer and a second intermediate interlayer insulating layer on the first intermediate interlayer insulating layer; and
before annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the second intermediate interlayer insulating layer is greater than an average hydrogen concentration of the first intermediate interlayer insulating layer.

2. The method of claim 1 ,
wherein the annealing of the transistor, the lower interlayer insulating layer and the hydrogen supply layer comprises diffusing hydrogen from the hydrogen supply layer into the lower interlayer insulating layer.

3. The method of claim 1 ,
wherein the annealing of the transistor, the lower interlayer insulating layer and the hydrogen supply layer is performed in a nitrogen atmosphere.

4. The method of claim 1 ,
wherein the memory cell comprises a magnetoresistance change material or a phase-change material.

5. The method of claim 1 , wherein:
prior to the annealing of the transistor, the lower interlayer insulating layer and the hydrogen supply layer, the lower interlayer insulating layer has an average hydrogen concentration that is less than an average hydrogen concentration of the hydrogen supply layer; and
after the annealing of the transistor, the lower interlayer insulating layer and the hydrogen supply layer, an upper interlayer insulating layer has an average hydrogen concentration that is less than the average hydrogen concentration of the hydrogen supply layer.

6. The method of claim 1 ,
wherein the hydrogen blocking layer comprises silicon nitride.

7. The method of claim 1 ,
wherein the hydrogen supply layer comprises silicon (Si), oxygen (O) and hydrogen (H).

8. The method of claim 1 ,
wherein a thickness of the hydrogen blocking layer is less, than a thickness of the hydrogen supply layer.

9. A method of manufacturing a memory device, the method comprising:
forming a transistor on a substrate;
forming a lower interlayer insulating layer covering the transistor;
forming at least one intermediate interlayer insulating layer on the lower interlayer insulating layer;
forming a hydrogen supply layer on the at least one intermediate interlayer insulating layer;
forming a hydrogen blocking layer on the hydrogen supply layer;
annealing the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer;
forming a memory cell on the hydrogen blocking layer after the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer; and
forming an upper interlayer insulating layer that surrounds the memory cell,
wherein the at least one intermediate interlayer insulating layer comprises a first intermediate interlayer insulating layer on the lower interlayer insulating layer and a second intermediate interlayer insulating layer on the first intermediate interlayer insulating layer; and
before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the second intermediate interlayer insulating layer is greater than an average hydrogen concentration of the first intermediate interlayer insulating layer.

10. The method of claim 9 , wherein:
before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the hydrogen supply layer is greater than an average hydrogen concentration of the lower interlayer insulating layer;
before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of at least one intermediate interlayer insulating layer is less than an average hydrogen concentration of the hydrogen supply layer; and
after the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the upper interlayer insulating layer is less than the average hydrogen concentration of the hydrogen supply layer.

11. The method of claim 9 ,
wherein, before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the second intermediate interlayer insulating layer is greater than an average hydrogen concentration of the lower interlayer insulating layer.

12. The method of claim 9 ,
wherein, before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, the average hydrogen concentration of the first intermediate interlayer insulating layer is less than an average hydrogen concentration of the hydrogen supply layer.

13. The method of claim 9 ,
wherein, after the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the hydrogen supply layer is less than an average hydrogen concentration of the hydrogen supply layer before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer.

14. The method of claim 9 ,
wherein, after the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer, an average hydrogen concentration of the lower interlayer insulating layer is greater than the average hydrogen concentration of the lower interlayer insulating layer before the annealing of the transistor, the lower interlayer insulating layer, the at least one intermediate interlayer insulating layer, and the hydrogen supply layer.

15. The method of claim 9 , further comprising, forming a conductive line and a contact connecting the conductive line and the transistor in the lower interlayer insulating layer.

16. The method of claim 9 , further comprising forming a contact penetrating through the hydrogen, supply layer and the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Jung-Hyun
• Kim Song-Yi
• Terai Masayuki

Classifications

• H10W20/097

  by thermally treating · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10P95/94 Primary

  Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma · CPC title

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title

• H01L45/06

  Electricity · mapped topic