Methods of forming a thyristor-based random access memory using fin structures and elevated layers

Patent metadata

Field	Value
Publication number	US-11094696-B2
Application number	US-201816217064-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	May 14, 2014
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.

First claim

What is claimed is:

1. A method of forming a thyristor-based memory cell, the method comprising:
forming a first fin structure and a second fin structure on a substrate;
forming an isolation region in a gap between the first fin structure and the second fin structure;
forming a well of a first polarity type in the substrate below the isolation region;
after forming the isolation region, forming a first region of a second polarity type in the first fin structure and a second region of the second polarity type in the second fin structure;
forming a first gate including a first gate dielectric and a first gate electrode layer in the gap over the isolation region;
after forming the first gate, forming a first dielectric sidewall spacer on a first sidewall of the first gate and a second dielectric sidewall spacer on a second sidewall of the first gate;
forming a first elevated layer of the first polarity type over the first region and adjacent to the first dielectric sidewall spacer and the first sidewall of the first gate;
forming a second elevated layer of the first polarity type over the second region and adjacent to the second dielectric sidewall spacer and the second sidewall of the first gate;
forming a third elevated layer of the second polarity type on the first elevated layer and adjacent to the first dielectric sidewall spacer and the first sidewall of the first gate; and
forming a fourth elevated layer of the second polarity type on the second elevated layer and adjacent to the second dielectric sidewall spacer and the second sidewall of the first gate;
wherein the well, the first region, the first elevated layer, and the third elevated layer form a first thyristor of the thyristor-based memory cell, and the well, the second region, the second elevated layer, and the fourth elevated layer form a second thyristor of the thyristor-based memory cell.

2. The method of claim 1 wherein the first region and the second region are concurrently formed by implanting dopants of the second polarity type into the substrate in the well.

3. The method of claim 1 wherein the first elevated layer and the second elevated layer are concurrently formed by selective epitaxial growth respectively over the first region and the second region.

4. The method of claim 3 wherein the third elevated layer and the fourth elevated layer are concurrently formed by selective epitaxial growth respectively over the first elevated layer and the second elevated layer.

5. The method of claim 1 wherein the third elevated layer and the fourth elevated layer are concurrently formed by selective epitaxial growth respectively over the first elevated layer and the second elevated layer.

6. The method of claim 1 further comprising:
after the third elevated layer and the fourth elevated layer are formed, removing the first gate to form an opening between the first dielectric sidewall spacer and the second dielectric sidewall spacer; and
forming a second gate in the opening.

7. The method of claim 6 wherein the second gate includes a second gate dielectric containing a high-k dielectric material and a second gate electrode containing a metal or a metal nitride.

8. The method of claim 1 wherein the first gate is formed after the first region and the second region are formed.

9. The method of claim 1 wherein the first gate is formed before the first elevated layer and the second elevated layer are formed.

10. The method of claim 9 wherein the first gate is formed after the first region and the second region are formed.

11. The method of claim 1 wherein the first gate is formed before the third elevated layer and the fourth elevated layer are formed.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Toh Eng Huat
• Tan Shyue Seng
• Quek Elgin Kiok Boone
• Shum Danny Pak-Chum

Classifications

• H10D18/01

  Manufacture or treatment · CPC title

• H10D18/00

  Thyristors · CPC title

• G11C11/39 Primary

  using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT} · CPC title

• H10B99/20 Primary

  comprising memory cells having thyristors · CPC title

• H01L27/1027 Primary

  Electricity · mapped topic