Methods of forming a conductive contact structure to a top electrode of an embedded memory device on an IC product and a corresponding IC product

Patent metadata

Field	Value
Publication number	US-11094585-B2
Application number	US-201916504737-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Jul 8, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

First claim

The invention claimed is:

1. A method of forming a conductive contact structure to a top electrode of a memory device, the method comprising:
forming a first layer of insulating material adjacent and in physical contact with a side surface of the top electrode of the memory device;
forming a second layer of insulating material above the first layer of insulating material;
forming an opening in the second layer of insulating material, the opening exposing an upper surface of the top electrode;
forming an internal sidewall spacer within the opening in the second layer of insulating material;
forming a third layer of insulating material above the second layer of insulating material; and
forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein the conductive contact structure includes a first portion that is surrounded by the internal sidewall spacer, and a second portion that is surrounded by and in physical contact with at least a portion of the third layer of insulating material,
wherein the first portion of the conductive contact structure surrounded by the internal sidewall spacer is in physical contact with an entire internal perimeter of the internal sidewall spacer such that the entire internal perimeter of the internal sidewall spacer encloses the first portion of the conductive contact structure.

2. The method of claim 1 , wherein forming the internal sidewall spacer comprises:
forming a conformal layer of a spacer material above the second layer of insulating material and in the opening; and
forming the internal sidewall spacer within the opening from a portion of the conformed layer of the spacer material.

3. The method of claim 1 , wherein, prior to forming the conductive contact structure, the method comprises:
forming additional insulation material above the second layer of insulating material, the additional insulation material filling a remaining portion of the opening in the second layer of insulating material that is not occupied by the internal sidewall spacer; and
forming at least a portion of a contact opening in the additional insulating material to expose at least a portion of the upper surface of the top electrode.

4. The method of claim 3 , wherein the portion of the contact opening within the internal sidewall spacer is formed in a self-aligned manner.

5. The method of claim 3 , wherein at least a portion of the contact opening abuts an upper surface of the internal sidewall spacer.

6. An integrated circuit product, comprising:
a memory cell comprising a top electrode;
a first layer of insulating material adjacent and in physical contact with a side surface of the top electrode,
a second layer of insulating material above the first layer of insulating material;
an opening in the second layer of insulating material, the opening exposing at least a portion of an upper surface of the top electrode;
an internal sidewall spacer positioned within the opening in the second layer of insulating material;
a third layer of insulating material above the second layer of insulating material; and
a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein the conductive contact structure includes a first portion that is surrounded by the internal sidewall spacer, and a second portion that is surrounded by and in physical contact with at least a portion of the third layer of insulating material,
wherein the first portion of the conductive contact structure surrounded by the internal sidewall spacer is in physical contact with an entire internal perimeter of the internal sidewall spacer such that the entire internal perimeter of the internal sidewall spacer encloses the first portion of the conductive contact structure.

7. The integrated circuit of claim 6 , wherein at least a portion of the conductive contact structure abuts an upper surface of the internal sidewall spacer.

8. The integrated circuit of claim 6 , wherein an upper surface of the internal sidewall spacer abuts both at least a portion of the third layer of insulating material and at least a portion of the conductive contact structure.

9. The integrated circuit of claim 6 , wherein one or more of the first, the second, and the third layers of insulating material includes a first material, and wherein the internal sidewall spacer includes a second material that is different from the first material.

10. The integrated circuit of claim 6 , wherein one or more of the first, the second, and the third layers of insulating material includes silicon dioxide, the internal sidewall spacer includes silicon nitride and the memory cell includes an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.

11. The integrated circuit of claim 6 , wherein the internal sidewall spacer further includes an upper surface that abuts both a portion of the third layer of insulating material and a portion of the conductive contact structure.

12. The method of claim 1 , wherein one or more of the first, second, and the third layers of insulating material comprises silicon dioxide, the internal sidewall spacer comprises silicon nitride and the memory device comprises one of an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.

13. The method of claim 1 , wherein an upper surface of the internal sidewall spacer further includes an upper surface that abuts both a portion of the third layer of insulating material and a portion of the conductive contact structure.

Assignees

• Globalfoundries Us Inc

Inventors

• Tran Xuan Anh
• Ramanathan Eswar
• Singh Sunil Kumar
• Kalaga Suryanarayana
• Regonda Suresh Kumar
• Tan Juan Boon

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title