Method and tool to improve efficiency and effectiveness of waterjet de-burr process

Patent metadata

Field	Value
Publication number	US-11090779-B2
Application number	US-201916442316-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Jun 14, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A waterjet nozzle is provided for deflashing a leadless package device. The waterjet nozzle has a central core having a conically shaped passage between a nozzle inlet, lying in a first plane, and a nozzle outlet, lying in a second plane. The nozzle includes a groove, in the waterjet nozzle, above a third plane defining an end of the waterjet nozzle, along a first line in the third plane. A tube connects the nozzle outlet to the groove. The nozzle includes a flange, lying below the third plane along a second line, in the third plane, intersecting the first line. The waterjet nozzle may be used to deflash a leadframe package by inserting the flange from a waterjet nozzle into a singulation cut on a lead frame; and injecting a waterjet through the conically-shaped passage from the nozzle inlet through the nozzle outlet.

First claim

I claim:

1. A method of forming a packaged semiconductor device, comprising:
conducting a partial sawing of a plurality of leads on a bottom side of a semiconductor package having a top side opposite said bottom side, the semiconductor package comprising a leadframe including a die pad, a semiconductor chip attached to said die pad, the plurality of leads extending about said die pad, each defining an opposing top and bottom surface and having an inner end, and an outer end, wherein said bottom surface and said outer end collectively define a bottom corner region, at least one conductive bond wire electrically connected to and extending between a bond pad on the semiconductor chip and a respective one of the leads from the plurality of leads, a mold compound around the die pad, the plurality of leads, the semiconductor chip, and the at least one conductive bond wire such that the bottom surface and the outer end are exposed, the partial sawing severing the plurality of leads and forming a partial cut in said mold compound;
performing a de-flash process using a pulsed waterjet, applied to the bottom side using a waterjet nozzle, the waterjet nozzle comprising: a central core having a conically shaped passage between a nozzle inlet, lying in a first plane, and a nozzle outlet lying in a second plane; an end, lying partial in a third plane, including a groove, above the third plane, along a first line in the third plane, the end further including a flange, lying below the third plane, along a second line on the third plane, intersecting the first line; and
a tube connecting the nozzle outlet to the groove,
wherein performing the de-flash process includes positioning the flange of the waterjet nozzle within the partial cut to increase flow resistance along the partial cut and direct flow from the waterjet within the groove;
aligning a saw blade for a second sawing, over the partial cut, from the top side; and
performing a second sawing reaching said partial cut to singulate the semiconductor package, wherein the second sawing does not touch the plurality of leads.

2. The method of forming a packaged semiconductor device as recited in claim 1 wherein the pulsed waterjet is applied, using varying amounts of pressure, to the bottom side.

3. The method of forming a packaged semiconductor device as recited in claim 2 wherein the varying amounts of pressure includes increasing the pressure applied to the waterjet.

4. The method of forming a packaged semiconductor device as recited in claim 2 wherein the varying amounts of pressure includes decreasing the pressure applied to the waterjet.

5. The method of forming a packaged semiconductor device, as recited in claim 1 , wherein the packaged semiconductor device is a leadless package device.

6. The method of forming a packaged semiconductor device, as recited in claim 5 , wherein the leadless package device is a Quad Flat No-Lead (QFN) package.

7. The method of forming a packaged semiconductor device as recited in claim 5 , wherein the leadless package device is a Small Outline No-Lead (SON) package.

8. The method of forming a packaged semiconductor device as recited in claim 1 , wherein performing the de-flash process includes positioning the waterjet nozzle such that the third plane of the waterjet nozzle registers with the bottom side of the semiconductor package with the flange within the groove.

9. A method of forming a plurality of packaged semiconductor devices, comprising:
partial sawing a plurality of leads of a leadframe strip for the plurality of packaged semiconductor devices, on a bottom side of the leadframe strip having a top side opposite said bottom side, the leadframe strip comprising the plurality of leads, a semiconductor chip for each of the plurality of packaged semiconductor devices, and a common mold compound around the plurality of leads and the semiconductor chip for each of the plurality of packaged semiconductor devices, the partial sawing severing the plurality of leads and forming a partial cut in the mold compound;
positioning a nozzle adjacent to the partial cut, the nozzle comprising:
a nozzle inlet fluidly connected to a fluid source;
a central core downstream of the nozzle inlet;
a nozzle outlet downstream of the central core;
a groove extending laterally from the nozzle outlet; and
a flange extending beyond an end of the nozzle outlet, wherein positioning the nozzle adjacent to the partial cut includes fitting the flange within the partial cut; and

performing a de-flash process to the severed plurality of leads using a pulsed jet applied to the bottom side at the partial cut with the nozzle, wherein the flange increases flow resistance along the partial cut to direct fluid flow within the groove.

10. The method of claim 9 , further comprising:
aligning a saw blade for a second sawing, over the partial cut, from the top side; and
performing a second sawing reaching said partial cut to singulate the plurality of packaged semiconductor devices, wherein the second sawing does not touch the plurality of leads.

11. The method of claim 9 , wherein the pulsed jet is applied using varying amounts of pressure, to the bottom side.

12. The method of claim 9 , wherein each of the plurality of packaged semiconductor devices is a leadless package device.

13. The method of claim 12 , wherein the leadless package device is a Quad Flat No-Lead (QFN) package.

14. The method of claim 12 , wherein the leadless package device is a Small Outline No-Lead (SON) package.

15. The method of claim 9 , wherein performing the de-flash process includes positioning the nozzle such that a bottom of the nozzle registers with the bottom side of the leadframe strip with the flange within the groove.

Assignees

• Texas Instruments Inc

Inventors

• Mohd Arshad Mohamad Ashraf

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/048

  Mechanical treatments, e.g. punching, cutting, deforming or cold welding · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title