Linear broadband transconductance amplifier

Patent metadata

Field	Value
Publication number	US-11088665-B2
Application number	US-201916590911-A
Country	US
Kind code	B2
Filing date	Oct 2, 2019
Priority date	Oct 2, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An amplifier circuit comprises a differential input stage and a differential output stage. The differential input stage includes a first differential input transistor pair coupled to a differential input of the amplifier circuit, and a second differential input transistor pair coupled to the differential input and the differential output stage; a degeneration impedance coupled between first transistors of the first and second differential input transistor pairs and second transistors of the first and second differential input transistor pairs; and a feedback circuit coupled to the first and second differential input transistor pairs and the degeneration impedance, wherein output current is provided from the differential input stage to the differential output stage by the feedback circuit and transition current is provided to the output stage by the second differential input transistor pair.

First claim

What is claimed is:

1. An amplifier circuit comprising:
a differential input stage and a differential output stage, the differential input stage including:
a first differential input transistor pair coupled to a differential input of the amplifier circuit, and a second differential input transistor pair coupled to the differential input and the differential output stage, wherein the first and second transistors of the first and second differential input transistor pairs are a first transistor type;
a degeneration impedance coupled between first transistors of the first and second differential input transistor pairs and second transistors of the first and second differential input transistor pairs; and
a feedback circuit coupled to the first and second differential input transistor pairs and the degeneration impedance, wherein output current is provided from the differential input stage to the differential output stage by the feedback circuit and transition current is provided to the output stage by the second differential input transistor pair, and wherein the feedback circuit includes transistors of a second transistor type complementary to the first transistor type.

2. The amplifier circuit of claim 1 , wherein the feedback circuit has a cut-off frequency bandwidth, and for input signals with frequencies greater than the cut-off frequency bandwidth, the output current is provided from the differential input stage to the differential output stage by the second differential input transistor pair.

3. The amplifier circuit of claim 1 , wherein the feedback circuit includes:
a first feedback loop including a first feedback loop transistor coupled to the first transistors of the first and second differential input transistor pairs; and
a second feedback loop including a second feedback loop transistor coupled to the second transistors of the first and second differential input transistor pairs;
wherein the first and second transistors of the second differential input transistor pair are a first transistor type and provide the transition current to the output stage, and the first and second feedback loop transistors are a second transistor type complementary to the first transistor type and provide the output current to the differential output stage.

4. The amplifier circuit of claim 3 , wherein the first transistor type is a PNP-type bipolar junction transistor (PNP-BJT), and the second transistor type is an NPN-type bipolar junction transistor (NPN-BJT).

5. The amplifier circuit of claim 3 , wherein the first transistor type is an NPN-type bipolar junction transistor (NPN-BJT), and the second transistor type is an PNP-type bipolar junction transistor (PNP-BJT).

6. The amplifier circuit of claim 3 ,
wherein transistors of the second differential input transistor pair and transistors of the first and second feedback loops are bipolar junction transistors (BJTs); and
an emitter of the first transistor of the second differential input transistor pair is coupled to a first current source and a collector of the first feedback loop transistor is coupled to the first current source; and
an emitter of the second transistor of the second differential input transistor pairs is coupled to a second current source and a collector of the second feedback loop transistor is coupled to the second current source.

7. The amplifier circuit of claim 3 , wherein the first transistor type is a P-type field effect transistor (PFET), and the second transistor type is an N-type field effect transistor (NFET).

8. The amplifier circuit of claim 3 , wherein the first transistor type is a N-type field effect transistor (NFET), and the second transistor type is P-type field effect transistor (PFET).

9. The amplifier circuit of claim 3 ,
wherein transistors of the second differential input transistor pair and transistors of the first and second feedback loops are field effect transistors (FETs); and
a source of the first transistor of the second differential input transistor pair is coupled to a first current source and a drain of the first feedback loop transistor is coupled to the first current source; and
a source of the second transistor of the second differential input transistor pairs is coupled to a second current source and a drain of the second feedback loop transistor is coupled to the second current source.

10. The amplifier circuit of claim 1 , wherein the first transistor of the second differential input transistor pair is a multiple of the first transistor of the first differential input transistor pair, and the second transistor of the second differential input transistor pair is a multiple of the second transistor of the first differential input transistor pair.

11. The amplifier circuit of claim 1 ,
wherein the feedback circuit includes two feedback loops each comprising two feedback circuit nodes within a feedback path and a feedback transistor, and the feedback transistor and the transistors of the first and second differential input transistor pairs are bipolar junction transistors (BJTs); and
wherein in each feedback loop a collector of the feedback transistor and an emitter of a transistor of the second differential input transistor pair are coupled to a first feedback circuit node of the feedback path, and a base of the feedback transistor and a collector of a transistor of the first differential input transistor pair are coupled to a second feedback circuit node of the feedback path.

12. A method of operating an amplifier circuit, the method comprising:
providing an output current from a differential input stage of the amplifier circuit to a differential output stage of the amplifier circuit;
regulating the output current using a feedback circuit connected to a first differential input transistor pair, a second differential input transistor pair, and a degeneration impedance; and
when an input signal to the amplifier circuit has a frequency within a cut-off frequency bandwidth of the feedback circuit, providing the output current to the differential output stage using the feedback circuit and providing transition current to the differential output stage using the second differential input transistor pair; and
when the input signal has a frequency greater than the cut-off bandwidth of the feedback circuit, providing the output current and the transient current to the output stage using the second differential input transistor pair.

13. The method of claim 12 , wherein providing the output current to the differential output stage using the feedback circuit includes providing the output current to the differential output stage using a feedback circuit differential transistor pair when an input signal to the amplifier circuit has a frequency within the cut-off bandwidth of the feedback circuit, wherein transistors of the feedback circuit differential transistor pair are of a transistor type complementary to a transistor type of the second differential input transistor pair.

14. The method of claim 12 , including changing from using a first-type bipolar junction transistor pair to provide current to the output stage to using a second-type bipolar junction transistor pair, complementary to the first type, to provide the current to the output stage in response to a change at the differential input of the amplifier circuit.

15. The method of claim 12 , including changing from using a first-type field effect transistor pair to provide current to the output stage to using a second-type field effect transistor pair, complementary to the first type, to provide the current to the output stage in response to a change at the diffe

Assignees

• Analog Devices Inc

Inventors

• Aksin Devrim Yilmaz

Classifications

• H03F1/34

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title

• H03F3/45488 Primary

  by using feedback means (H03F3/4578 takes precedence) · CPC title

• H03F2203/45632

  the LC comprising one or more capacitors coupled to the LC by feedback · CPC title

• H03F1/3211 Primary

  in differential amplifiers · CPC title

• H03F2203/45392

  the AAC comprising resistors in the source circuit of the AAC before the common source coupling · CPC title