Circuit and method for protecting a voltage regulating circuit against electrostatic discharges

Patent metadata

Field	Value
Publication number	US-11088536-B2
Application number	US-201916690644-A
Country	US
Kind code	B2
Filing date	Nov 21, 2019
Priority date	Aug 4, 2016
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a first terminal and a second terminal configured to be coupled to respective antenna terminals;
a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal;
a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
an electrostatic discharge (ESD) detection circuit configured to sense an ESD event at said first output of the rectification circuit and in response thereto assert a control signal; and
a control circuit configured to control a voltage at the control terminal of the first transistor which places the transistor in an off state by selectively connecting the control terminal of the first transistor to one of the first and second terminals in response to assertion of the control signal.

2. The integrated circuit of claim 1 , further including an ESD protection transistor coupled between the first and second outputs of the rectification circuit and selectively actuated in response to assertion of the control signal.

3. The integrated circuit of claim 1 , further comprising a processing circuit having power supply terminals connected to the first and second outputs of the rectification circuit.

4. The integrated circuit of claim 1 , further comprising a comparator circuit configured to compare a voltage at the first output of the rectification circuit to a reference voltage and generate a further control signal applied to the control terminal of the transistor.

5. The integrated circuit of claim 1 , wherein the control circuit is configured to:
apply a voltage from the second terminal to the control terminal of the first transistor in response to assertion of the control signal when the sensed ESD event arises from a flow of an ESD pulse from the first terminal towards the second terminal; and
apply a voltage from the first terminal to the control terminal of the first transistor in response to assertion of the control signal when the sensed ESD event arises from a flow of an ESD pulse from the second terminal towards the first terminal.

6. The integrated circuit of claim 1 , wherein the control circuit comprises:
a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
wherein the second through fifth transistors are connected in series between the first and the second terminals;
wherein the second transistor has a control terminal connected to the second terminal and an electrode connected to the first terminal;
wherein the third transistor and the fourth transistor having respective control terminals connected to receive said control signal and a common electrode connected to the control terminal of said first transistor; and
wherein the fifth transistor has a control terminal connected to the first terminal and an electrode connected to the second terminal.

7. The integrated circuit of claim 2 , wherein a first conduction terminal of the ESD protection transistor is directly electrically connected to the first output and a second conduction terminal of the ESD protection transistor is directly electrically connected to the second output.

8. An integrated circuit, comprising:
a first terminal and a second terminal configured to be coupled to respective antenna terminals;
a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal; a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
an electrostatic discharge (ESD) detection circuit configured to generate a control signal having a logic state indicative of detection of an ESD event at said first output of the rectification circuit; and
a control circuit coupled to said control terminal and configured to respond to said logic state for the control signal due to detection of the ESD event by selectively connecting the control terminal of the first transistor to one of the first and second terminals in order to control the first transistor to be in an off state.

9. The integrated circuit of claim 8 , further comprising further comprising a comparison circuit configured to control conductivity of said first transistor in response to a comparison of a voltage at the first output of the rectification circuit to a reference voltage.

10. The integrated circuit of claim 8 , further including an ESD protection transistor coupled between the first and second outputs of the rectification circuit and selectively actuated in response to assertion of the control signal.

11. The integrated circuit of claim 8 , further comprising a processing circuit having power supply terminals connected to the first and second outputs of the rectification circuit.

12. The integrated circuit of claim 8 , wherein the control circuit is configured to apply a voltage from the second terminal to the control terminal of the first transistor in response to assertion of the control signal, wherein said voltage from the second terminal places the first transistor in the off state.

13. The integrated circuit of claim 12 , wherein said voltage is applied by the control circuit in response to the sensed ESD event arising from a flow of an ESD pulse from the first terminal towards the second terminal.

14. The integrated circuit of claim 8 , wherein the control circuit is configured to apply a voltage from the first terminal to the control terminal of the first transistor in response to assertion of the control signal, wherein said voltage from the first terminal places the first transistor in the off state.

15. The integrated circuit of claim 14 , wherein said voltage is applied by the control circuit in response to the sensed ESD event arising from a flow of an ESD pulse from the second terminal towards the first terminal.

16. The integrated circuit of claim 8 , wherein the control circuit comprises:
a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
wherein the second through fifth transistors are connected in series between the first and the second terminals;
wherein the second transistor has a control terminal connected to the second terminal and an electrode connected to the first terminal;
wherein the third transistor and the fourth transistor having respective control terminals connected to receive said control signal and a common electrode connected to the control terminal of said first transistor; and
wherein the fifth transistor has a control terminal connected to the first terminal and an electrode connected to the second terminal.

17. The integrated circuit of claim 10 , wherein a first conduction terminal of the ESD protection transistor is directly electrically connected to the first output and a second conduction terminal of the ESD protection transistor is directly electrically connected to the second output.

18. An integrated circuit, comprising:
a first terminal and a second terminal configured to be coupled to respective antenna terminals;
a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal;
a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
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Assignees

• St Microelectronics Rousset

Inventors

• Demange Nicolas

Classifications

• H10D89/611

  using diodes as protective elements · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H9/041

  using a short-circuiting device · CPC title