Display apparatus and method of manufacturing the same

US11088284B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11088284-B2
Application numberUS-201815871468-A
CountryUS
Kind codeB2
Filing dateJan 15, 2018
Priority dateJun 16, 2017
Publication dateAug 10, 2021
Grant dateAug 10, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display apparatus includes: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between a first area and a second area and bent along a bending axis are defined; a first thin-film transistor (“TFT”) and a second TFT; and a first conductive layer and a second conductive layer. The first TFT includes: a first active layer including polycrystalline silicon; a first gate electrode; and a first electrode disposed at a level which is the same as a level of the first conductive layer, and the second TFT includes: a second active layer including an oxide semiconductor; a second gate electrode; and a second electrode disposed at a level which is the same as a level of the second conductive layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A display apparatus comprising: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between the first area and the second area and bent along a bending axis are defined; a first thin-film transistor disposed in the first area; a second thin-film transistor disposed in the first area; and a first conductive layer extending from the first area through the bending area to the second area; a second conductive layer extending from the first area through the bending area to the second area, wherein the first conductive layer and the second conductive layer are disposed at different levels from each other, wherein the first thin-film transistor comprises: a first active layer comprising polycrystalline silicon; a first gate electrode insulated from the first active layer; and a first electrode connected to the first active layer and disposed at the same level as the first conductive layer, and the second thin-film transistor comprises: a second active layer comprising an oxide semiconductor; a second gate electrode insulated from the second active layer; and a second electrode connected to the second active layer and disposed at a level, which is the same as the level of the second conductive layer. 2. The display apparatus of claim 1 , further comprising: a display device driven by the first thin-film transistor and the second thin-film transistor, wherein the first thin-film transistor is a driving thin-film transistor which transmits a driving current to the display device. 3. The display apparatus of claim 1 , further comprising: a first interlayer insulating layer disposed on the substrate to cover the first gate electrode, wherein the second active layer is disposed on the first interlayer insulating layer. 4. The display apparatus of claim 3 , further comprising: a second interlayer insulating layer disposed on the first interlayer insulating layer to cover the second gate electrode, wherein the first electrode is disposed on the second interlayer insulating layer. 5. The display apparatus of claim 4 , further comprising: a planarization layer disposed on the second interlayer insulating layer to cover the first electrode, wherein the second electrode is disposed on the planarization layer. 6. The display apparatus of claim 1 , further comprising: a connection electrode electrically connected to the first electrode and disposed at a level, which is the same as a level of the second electrode. 7. The display apparatus of claim 1 , wherein the first conductive layer and the second conductive layer are electrically connected to each other, and each of the first conductive layer and the second conductive layer transmits a driving signal to at least one of the first thin-film transistor and the second thin-film transistor. 8. The display apparatus of claim 7 , wherein a plurality of through-holes is defined in each of the first conductive layer and the second conductive layer. 9. The display apparatus of claim 1 , wherein each of the first conductive layer, the second conductive layer, the first electrode and the second electrode comprises aluminum (Al). 10. The display apparatus of claim 1 , further comprising: a bending organic layer disposed between the substrate and the first conductive layer, wherein at least a portion of the bending organic layer is disposed in the bending area. 11. The display apparatus of claim 1 , further comprising: a capacitor electrode disposed on the first gate electrode to face the first gate electrode, wherein the second active layer is disposed on a layer that is disposed over the capacitor electrode.

Assignees

Inventors

Classifications

  • Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

  • Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

  • Three-dimensional [3D] integrated devices · CPC title

  • integrated with passive devices, e.g. auxiliary capacitors · CPC title

  • having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

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What does patent US11088284B2 cover?
A display apparatus includes: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between a first area and a second area and bent along a bending axis are defined; a first thin-film transistor (“TFT”) and a second TFT; and a first conductive layer and a second conductive layer. The first TFT includes: a first active layer including polycrystalli…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 10 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).