Semiconductor device and method for fabricating a semiconductor device

US11088105B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11088105-B2
Application numberUS-201916695866-A
CountryUS
Kind codeB2
Filing dateNov 26, 2019
Priority dateNov 28, 2018
Publication dateAug 10, 2021
Grant dateAug 10, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a carrier comprising a die pad and a contact; a semiconductor die comprising a first main side and an opposing second main side, the semiconductor die being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip comprising a first contact region and a second contact region, the first contact region being attached to the first main side of the semiconductor die by a second solder joint and the second contact region being attached to the contact by a third solder joint, wherein the first contact region has a convex shape facing towards the first main side of the semiconductor die such that a distance between the first main side and the first contact region increases from a base of the convex region towards an edge of the first contact region, wherein the base runs along a line that runs substantially perpendicular to a longitudinal axis of the contact clip, wherein the contact clip has a uniform width along the longitudinal axis, wherein the line runs along the entire width. 2. The semiconductor device of claim 1 , wherein the distance monotonically increases from the base towards the edge. 3. The semiconductor device of claim 2 , wherein the distance monotonically increases continuously from the base towards the edge. 4. The semiconductor device of claim 1 , wherein the line coincides with a center axis of the semiconductor die within a margin of error of 200 μm or less. 5. The semiconductor device of claim 1 , wherein the second contact region of the contact clip comprises a bent-down end portion comprising a cut surface, and wherein the cut surface faces the contact. 6. The semiconductor device of claim 1 , wherein the first contact region and the second contact region of the contact clip are straight. 7. The semiconductor device of claim 1 , wherein the first solder joint is flat such that a vertical distance of the second main side of the semiconductor die to the die pad is within a margin of error of 15 μm or less. 8. A semiconductor device, comprising: a carrier comprising a die pad and a contact; a semiconductor die comprising a first main side and an opposing second main side, the semiconductor die being attached to the die pad by a first solder joint such that the second main side faces the die pad; a contact clip comprising a first contact region and a second contact region, the first contact region being attached to the first main side of the semiconductor die by a second solder joint and the second contact region being attached to the contact by a third solder joint, wherein the first contact region has a convex shape facing towards the first main side of the semiconductor die such that a distance between the first main side and the first contact region increases from a base of the convex region towards an edge of the first contact region, wherein the base runs along a line that runs substantially perpendicular to a longitudinal axis of the contact clip, and wherein the convex shape is a V shape with a rounded tip. 9. The semiconductor device of claim 8 , wherein a surface curvature of the first contact region is free of discontinuities. 10. The semiconductor device of claim 8 , wherein a tilt angle between the first main side of the semiconductor die and a leg of the V shape is in a range of 3° to 15°. 11. The semiconductor device of claim 8 , wherein the second contact region of the contact clip has a gull wing shape. 12. The semiconductor device of claim 8 , wherein the second contact region of the contact clip comprises a bent-down end portion comprising a cut surface, and wherein the cut surface faces the contact. 13. The semiconductor device of claim 8 , wherein the first contact region and the second contact region of the contact clip are straight. 14. The semiconductor device of claim 8 , wherein the first solder joint is flat such that a vertical distance of the second main side of the semiconductor die to the die pad is within a margin of error of 15 μm or less. 15. A method for fabricating a semiconductor device, the method comprising: providing a carrier comprising a die pad and a contact; depositing a first solder deposit on the die pad and a third solder deposit on the contact; arranging a semiconductor die comprising a first main side and an opposing second main side on the first solder deposit such that the second main side faces the die pad; depositing a second solder deposit on the first main side of the semiconductor die; arranging a contact clip comprising a first contact region and a second contact region over the semiconductor die such that the first contact region contacts the second solder deposit and the second contact region contacts the third solder deposit; and soldering the first, second and third solder deposits, wherein the first contact region has a convex shape facing towards the first main side of the semiconductor die such that a distance between the first main side and the first contact region increases from a base of the convex region towards an edge of the first contact region, wherein the base runs along a line that runs substantially perpendicular to a longitudinal axis of the contact clip, wherein the contact clip has a uniform width along the longitudinal axis, wherein the line runs along the entire width. 16. The method of claim 15 , wherein the first, second and third solder deposits are soldered simultaneously. 17. The method of claim 15 , wherein the distance monotonically increases from the base towards the edge. 18. The method of claim 17 , wherein the distance monotonically increases continuously from the base towards the edge. 19. The method of claim 15 , wherein the line coincides with a center axis of the semiconductor die within a margin of error of 200 μm or less. 20. A method for fabricating a semiconductor device, the method comprising: providing a carrier comprising a die pad and a contact; depositing a first solder deposit on the die pad and a third solder deposit on the contact; arranging a semiconductor die comprising a first main side and an opposing second main side on the first solder deposit such that the second main side faces the die pad; depositing a second solder deposit on the first main side of the semiconductor die; arranging a contact clip comprising a first contact region and a second contact region over the semiconductor die such that the first contact region contacts the second solder deposit and the second contact region contacts the third solder deposit; and soldering the first, second and third solder deposits, wherein the first contact region has a convex shape facing towards the first main side of the semiconductor die such that a distance between the first main side and the first contact region increases from a base of the convex region towards an edge of the first contact region, wherein the base runs along a line that runs substantially perpendicular to a longitudinal axis of the contact clip, wherein the convex shape is a V shape with a rounded tip.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Packaging processes not covered by the other groups of this subclass · CPC title

  • Soldering or alloying · CPC title

  • Cross-sectional shape · CPC title

  • Shapes of strap connectors · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11088105B2 cover?
A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder …
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W72/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 10 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).