Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same

Patent metadata

Field	Value
Publication number	US-11087839-B2
Application number	US-202016802803-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Jul 31, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array having a vertical stack-type structure including a semiconductor layer and a resistance change layer, the memory cell array including a plurality of memory cells that each include a corresponding portion of the semiconductor layer and a corresponding portion of the resistance change layer; and
a control logic,
the control logic, in a read operation, being configured to apply a first voltage to a non-select memory cell and the first voltage has a level to turn on current only in the corresponding portion of the semiconductor layer of the non-select memory cell,
the control logic, during the read operation, being configured to apply a second voltage to a select memory cell and the second voltage has a level to turn on current in both the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell, and
the non-select memory cell and the select memory cell being among the plurality of memory cells of the memory cell array; and

a bit line connected to the memory cell array, the bit line being configured to apply a read voltage to the select memory cell during the read operation, wherein
an absolute value of the second voltage is greater than an absolute value of a third voltage, and
the third voltage has a level to turn on current in the corresponding portion of the resistance change layer of the select memory cell, based on the control logic applying the third voltage to the select memory cell.

2. The memory device of claim 1 , wherein,
the control logic, in a program operation, is configured to apply the first voltage to the non-select memory cell to turn on current only in the corresponding portion of the semiconductor layer of the non-select memory cell, and
the control logic, in the program operation, is configured to apply the second voltage to the select memory cell to turn on current in both the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell, and
the bit line is configured to apply a program voltage to the select memory cell during the program operation.

3. The memory device of claim 1 , wherein the second voltage has a magnitude so that the corresponding portion of the semiconductor layer of the select memory cell has a resistance magnitude in a range of 10 4 Ω through 10 12 Ω, based on the control logic applying the second voltage to the select memory cell.

4. The memory device of claim 1 , wherein the second voltage has a magnitude so that a ratio of a maximum value to a minimum value of a composite resistance of the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell is 10 or less, based on the control logic applying the second voltage to the select memory cell.

5. The memory device of claim 1 , wherein the second voltage has a magnitude so that a resistance of the corresponding portion of the semiconductor layer corresponding of the select memory cell is equal to or greater than a minimum resistance of the corresponding portion of the resistance change layer of the select memory cell, based on the control logic applying the second voltage to the select memory cell.

6. The memory device of claim 1 , wherein the second voltage has a magnitude so that a resistance of the corresponding portion of the semiconductor layer corresponding of the select memory cell is equal to or less than a maximum resistance of the corresponding portion of the resistance change layer corresponding to the select memory cell, based on the control logic applying the second voltage to the select memory cell.

7. The memory device of claim 1 , wherein the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell have a parallel connection structure.

8. The memory device of claim 1 , wherein the memory cell array includes:
the semiconductor layer extending in a first direction;
a plurality of gates and a plurality of insulating layers extending in a second direction perpendicular to the first direction and alternately disposed to each other;
a gate insulating layer extending in the first direction between the plurality of gates, the plurality of insulating layers, and the semiconductor layer; and
the resistance change layer extending in the first direction on the semiconductor layer.

9. The memory device of claim 8 , wherein the resistance change layer is spaced apart from the gate insulating layer with the semiconductor layer therebetween.

10. The memory device of claim 1 , wherein the resistance change layer contacts the semiconductor layer.

11. The memory device of claim 1 , wherein the resistance change layer includes a material in which a resistance is changed by a phenomenon of oxygen vacancies or a current conduction mechanism by trap/detrap of electrons.

12. The memory device of claim 1 , wherein the resistance change layer includes one or more transition metal oxides, one or more transition metal nitrides, or both the one or more transition metal oxides and one or more transition metal nitrides.

13. A method of operating a non-volatile memory device, the method comprising:
applying a first voltage to a non-select memory cell among a plurality of memory cells of a memory cell array, the memory cell array having a vertical stack-type structure including a semiconductor layer and a resistance change layer, each of the plurality of memory cells including a corresponding portion of the semiconductor layer and a corresponding portion of the resistance change layer, and the first voltage having a level to turn on current only in the corresponding portion of the semiconductor layer of the non-select memory cell;
applying a second voltage to a select memory cell among the plurality of memory cells of the memory cell array, the second voltage having a level to turn on current in both the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell; and
applying a read voltage to the select memory cell of the memory cell array, wherein
an absolute value of the second voltage is greater than a third voltage, and
the third voltage has a level to turn on current in the corresponding portion of the resistance change layer of the select memory cell of the memory cell array, based on applying the third voltage to the select memory cell.

14. The method of claim 13 , wherein the second voltage has a magnitude so that a ratio of a maximum value to a minimum value of a composite resistance of the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell is 10 or less, based on applying the second voltage to the select memory cell.

15. The method of claim 13 , wherein the second voltage has a magnitude so that a resistance of the corresponding portion of the semiconductor layer of the select memory cell is equal to or greater than the minimum resistance of the corresponding portion of the resistance change layer of the select memory cell, based on applying the second voltage to the select memory cell.

16. The method of claim 13 , wherein the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the selected memory cell have a parallel connection structure.

17. A memory device comprising:
a substrate;

Assignees

• Samsung Electronics Co Ltd
• Seoul Nat Univ R&Db Foundation

Inventors

• Yoon Jungho
• Hwang Cheol Seong
• Mizusaki Soichiro
• Cho Youngjin

Classifications

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title