System comprising non-volatile memory device and one or more persistent memory devices in respective fault domains

Patent metadata

Field	Value
Publication number	US-11086739-B2
Application number	US-201916555516-A
Country	US
Kind code	B2
Filing date	Aug 29, 2019
Priority date	Aug 29, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A system includes a host processor, a volatile memory device coupled to the host processor, and at least a first persistent memory device coupled to the host processor. The host processor is configured to execute one or more applications. The volatile memory device and the first persistent memory device are in respective distinct fault domains of the system, and at least one of a plurality of data objects generated by a given one of the applications is accessible from multiple distinct storage locations in respective ones of the distinct fault domains. For example, the host processor and the volatile memory device may be in a first one of the distinct fault domains and the first persistent memory device may be in a second one of the distinct fault domains. The data object remains accessible in one of the fault domains responsive to a failure in another of the fault domains.

First claim

What is claimed is:

1. A system comprising:
a host processor;
a volatile memory device coupled to the host processor;
at least a first persistent memory device coupled to the host processor;
the host processor being configured to execute one or more applications;
the volatile memory device and the first persistent memory device being in respective distinct fault domains of the system;
wherein at least one of a plurality of data objects generated by a given one of the applications is accessible from multiple distinct storage locations in respective ones of the distinct fault domains; and
wherein the host processor, the volatile memory device and the first persistent memory device are part of a first application server of the system, the first application server thereby comprising at least a portion of each of the distinct fault domains.

2. The system of claim 1 wherein the host processor and the volatile memory device are in a first one of the distinct fault domains and the first persistent memory device is in a second one of the distinct fault domains.

3. The system of claim 2 wherein the data object remains accessible in one of the first and second fault domains responsive to a failure in the other one of the first and second fault domains.

4. The system of claim 1 wherein the first persistent memory device comprises:
a multi-ported host bus adaptor comprising a memory bridge coupled to a persistent memory;
a first one of the ports of the multi-ported host bus adaptor being coupled to the host processor and providing a cache coherent interface configured to transport cache lines to and from the host processor; and
a second one of the ports of the multi-ported host bus adaptor being coupled to a network of the system and being configured to support data transfers over the network to and from other processing devices of the system;
wherein responsive to a failure in a first one of the fault domains comprising the host processor and the volatile memory device, the first persistent memory device remains accessible in a second one of the fault domains via the second port of the multi-ported host bus adaptor.

5. The system of claim 4 wherein an inbound data transfer received via the second port of the multi-ported host bus adaptor causes a cache invalidation command to be transferred via the first port of the multi-ported host bus adaptor to the host processor.

6. The system of claim 4 wherein the memory bridge of the multi-ported host bus adaptor implements local processing functionality including one or more of:
storage protocol bridging;
command initiation and response for the first and second ports;
acceleration for at least one of encryption, decryption, compression and decompression;
intelligent offloading of data objects from the persistent memory to other storage devices of the system;
movement of data objects between multiple storage tiers of the system; and
movement of data objects between multiple application servers of the system responsive to a failure in one of the application servers.

7. The system of claim 1 further comprising one or more additional application servers interconnected with one another and with the first application server via a network of the system.

8. The system of claim 7 wherein responsive to a failure in at least one of the host processor and the volatile memory device of the first application server, a particular one of the data objects generated by the given application and stored in a storage location of the first persistent memory device remains accessible over the network to at least one of the one or more additional application servers.

9. The system of claim 1 wherein the system further comprises a second persistent memory device coupled to the host processor and wherein the volatile memory, the first persistent memory device and the second persistent memory device are in respective first, second and third distinct fault domains of the system.

10. The system of claim 9 wherein a particular one of the data objects generated by the given application is stored in respective distinct storage locations of the first and second persistent memory devices.

11. The system of claim 10 wherein responsive to a failure in one of the first and second persistent memory devices, the data object remains accessible in the other one of the first and second persistent memory devices.

12. The system of claim 9 wherein one or more of the data objects are controllably offloaded from the first and second persistent memory devices to one or more other storage devices of the system under specified conditions.

13. The system of claim 12 wherein one or more of the data objects are controllably restored from the one or more other storage devices to the first and second persistent memory devices under specified conditions.

14. The system of claim 1 wherein data is transferred across the fault domains using high-speed serial interconnects provisioned with direct current blocking capacitors to prevent faults from crossing between the fault domains.

15. A method comprising:
to execute one or more applications utilizing a host processor of a system;
to provide accessibility to at least one of a plurality of data objects generated by a given one of the applications from multiple distinct storage locations in respective distinct fault domains of the system;
a first one of the distinct fault domains comprising a volatile memory device coupled to the host processor; and
a second one of the distinct fault domains comprising a first persistent memory device coupled to the host processor;
wherein the data object remains accessible in one of the first and second fault domains responsive to a failure in the other one of the first and second fault domains; and
wherein the host processor, the volatile memory device and the first persistent memory device are part of a first application server of the system, the first application server thereby comprising at least a portion of each of the distinct fault domains.

16. The method of claim 15 wherein the system further comprises one or more additional application servers interconnected with one another and with the first application server via a network of the system.

17. The method of claim 15 wherein the system further comprises a second persistent memory device coupled to the host processor and wherein the volatile memory, the first persistent memory device and the second persistent memory device are in respective first, second and third distinct fault domains of the system, a particular one of the data objects generated by the given application being stored in respective distinct storage locations of the first and second persistent memory devices, and wherein responsive to a failure in one of the first and second persistent memory devices, the data object remains accessible in the other one of the first and second persistent memory devices.

18. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by a system comprising a host processor, a volatile memory device coupled to the host processor, and at least a first persistent memory device coupled to the host processor, causes the system:
to execute one or more applications utilizing the host processor;
to provide accessibility to at least one of a plurality of data objects generated by a given one of the applications from multiple distinct storage locations in respective distinct fault do

Assignees

• Emc Ip Holding Co Llc

Inventors

• Robillard Michael
• Michaud Adrian
• Savic Dragan

Classifications

• H04L69/40

  for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection (management of faults, events, alarms or notifications in data switching networks H04L41/06) · CPC title

• H04L67/1097

  for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/203 Primary

  using migration · CPC title

• G06F11/3034

  where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title