Mass storage cache in non volatile level of multi-level system memory

Patent metadata

Field	Value
Publication number	US-2018095884-A1
Application number	US-201615282478-A
Country	US
Kind code	A1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.

First claim

1 . An apparatus, comprising:
a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory, the non volatile region of the system memory to support execution of program code directly out of the non volatile region system memory.

2 . The apparatus of claim 1 wherein the logic circuitry comprises address indirection table circuitry comprised of embedded memory circuitry within the memory controller.

3 . The apparatus of claim 1 wherein the memory controller is to service a read call to mass storage with a buffer desired by the read call if the buffer is resident in the mass storage cache.

4 . The apparatus of claim 1 wherein the logic circuitry is to cause a null response to a request to free system memory space in the mass storage cache.

5 . The apparatus of claim 1 wherein the logic circuitry is to allocate a buffer in the non-volatile region of the system memory if the buffer is expected to be a target of a write call.

6 . The apparatus of claim 1 wherein the memory controller is to treat a buffer that is resident in the mass storage cache as being within system memory in response to an attempt to write to the buffer's physical address if no previous attempt has been made to write to the buffer's data while the buffer was within the mass storage cache.

7 . The apparatus of claim 1 wherein the memory controller is a far memory controller.

8 . A machine readable storage medium containing program code that when processed by a computing system causes the system to perform a method, the method comprising:
performing a write call on a buffer within a system memory having a non volatile region and a mass storage cache within the non volatile region, the performing of the write call comprising: executing a cache line flush instruction to direct any cache lines of the buffer within a processor level cache to a memory controller; executing a fence instruction to indicate that program execution shall not continue until the cache lines have been written to system memory; executing a commit instruction to commit the buffer's contents to the mass storage cache.

9 . The machine readable storage medium of claim 8 wherein the method further comprises executing respective cache line flush, fence and commit instructions to commit meta data of the mass storage cache to the mass storage cache.

10 . The machine readable storage medium of claim 8 wherein the method further comprises marking the buffer as read only as part of its commitment to the mass storage cache.

11 . The machine readable storage medium of claim 8 wherein the method further comprises updating meta data of the mass storage cache to reflect the buffer's presence in the mass storage cache.

12 . The machine readable storage medium of claim 8 wherein the method further comprises marking the buffer as read only in the mass storage cache and handling a fault in response to an attempt to write to the buffer as follows:
if the buffer's content is not dirty, changing a status of the buffer's content from being in the mass storage cache to being in system memory;
if the buffer's content is dirty, request space in system memory for the buffer's content, if the request is successful copy the buffer's content into the space in system memory, if the request is not successful then cleaning the buffer's content.

13 . The machine readable storage medium of claim 8 wherein the method further comprises writing a second buffer in the system memory that is a target of the write call into mass storage because an attempt to allocate space for the buffer in the non volatile region failed.

14 . The machine readable storage medium of claim 8 further comprising allocating a buffer that is expected to be a target of a write call into the non volatile region.

15 . The machine readable medium of claim 8 further comprising changing a status of a buffer from being read only in the mass storage cache to being writeable in system memory.

16 . A computing system, comprising:
one or more processing cores; a networking interface; a multi-level system memory; a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of the multi-level system memory, the multi-level system memory to support execution of program code by way of cache line granularity accesses to the multi-level system memory.

17 . The computing system of claim 16 wherein the logic circuitry comprises address indirection table circuitry comprised of embedded memory circuitry within the memory controller.

18 . The computing system of claim 16 wherein the memory controller is to service a read call to mass storage with a buffer desired by the read call if the buffer is resident in the mass storage cache.

19 . The computing system of claim 16 wherein the logic circuitry is to cause a null response to a desire to free memory space in the mass storage cache.

20 . The computing system of claim 16 wherein the logic circuitry is to allocate a buffer in the non-volatile region of the multi-level system memory if the buffer is expected to be a target of a write call.

21 . The computing system of claim 16 wherein the memory controller is to treat a buffer that is resident in the mass storage cache as being within system memory in response to an attempt to write to the buffer's physical address if no previous attempt has been made to write to the buffer's data while the buffer was within the mass storage cache.

22 . The computing system of claim 16 wherein the memory controller is a far memory controller.

Assignees

• Intel Corp

Inventors

• Kaminski Maciej
• Wysocki Piotr
• Ptak Slawomir

Classifications

• G06F12/0873 Primary

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/271

  Non-uniform cache access [NUCA] architecture · CPC title

• G06F2212/313

  In storage device · CPC title