Mapping consecutive logical block addresses to consecutive good blocks in memory device

Patent metadata

Field	Value
Publication number	US-11086539-B2
Application number	US-201916659353-A
Country	US
Kind code	B2
Filing date	Oct 21, 2019
Priority date	Oct 21, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

First claim

We claim:

1. An apparatus, comprising:
a first set of blocks arranged in a first block sequence in a first plane on a substrate, each block in the first set of blocks comprising memory cells; and
a circuit configured to map consecutive logical block addresses in a first sequence of logical block addresses to consecutive good blocks in the first block sequence; wherein for each bad block of one or more bad blocks in the first block sequence, the mapping substitutes a next available good block in the first block sequence; wherein:
the first set of blocks is arranged in a trimmed die which is among stacked dice, the stacked dice comprise an untrimmed die, the trimmed die having a number M blocks, and the untrimmed die having number N blocks, where M<N; and
the circuit comprises a bad block register which identifies N-M trimmed physical blocks of the trimmed die as bad blocks.

2. The apparatus of claim 1 , wherein:
the circuit is configured to perform the mapping of the consecutive logical block addresses in the first sequence of logical block addresses, starting from a first logical block address in the first sequence of logical block addresses and continuing to a last logical block address in the first sequence of logical block addresses, to consecutive good blocks in the first block sequence, starting from an initial good block in the first block sequence and continuing to a last good block in the first block sequence which is used in the mapping of the consecutive logical block addresses in the first sequence.

3. The apparatus of claim 1 , further comprising:
a second set of blocks arranged in a second plane on the substrate in a second block sequence, each block in the second set of blocks comprising memory cells, wherein:
the circuit is configured to map consecutive logical block addresses in a second sequence of logical block addresses to consecutive good blocks in the second block sequence, wherein for each bad block of one or more bad blocks in the second block sequence, the mapping substitutes a next available good block in the second block sequence;
the first sequence of logical block addresses and the second sequence of logical block addresses extend in a range of logical block addresses; and
each pair of consecutive logical block addresses in the range of logical block addresses comprises a logical block address from the first sequence of logical block addresses and a logical block address from the second sequence of logical block addresses, and is mapped to a pair of good blocks comprising a good block from the first block sequence and a good block from the second block sequence.

4. The apparatus of claim 3 , wherein:
the circuit is configured to receive a request to perform an operation, the request comprising a pair of consecutive logical block addresses, and in response to the request, perform the operation concurrently on a corresponding pair of good blocks comprising a good block from the first block sequence and a good block from the second block sequence.

5. The apparatus of claim 1 , wherein:
for each bad block of the one or more bad blocks in the first block sequence, the next available good block in the first block sequence comprises a good block which is not a substitute for another bad block.

6. The apparatus of claim 1 , wherein:
a position of each logical block address in the first sequence of logical block addresses corresponds to a position of a block in the first block sequence; and
to map a selected logical block address in the first sequence of logical block addresses to a block in the first block sequence, the circuit is configured to:
determine a block having a position in the first block sequence corresponding to the position of the selected logical block address in the first sequence of logical block addresses;
determine a number X>1 of bad blocks before, and including, the corresponding block in the sequence;
determine a number Y of bad blocks in the X blocks after the corresponding block in the sequence; and
map the selected logical block address to a block which is X+Y blocks after the corresponding block in the first block sequence, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block alter the block which is X+Y blocks after the corresponding block.

7. The apparatus of claim 1 , wherein:
a position of each logical block address in the first sequence block addresses corresponds to a position of a block in the first block sequence; and
to map a selected logical block address in the first sequence of logical block addresses to a block in the first block sequence, the circuit is configured to:
determine a block having a position in the first block sequence corresponding to the position of the selected logical block address in the first sequence of logical block addresses;
determine whether the corresponding block is a bad block and whether there are any bad blocks before the corresponding block in the sequence; and
map the selected logical block address to the corresponding block if the corresponding block is not a bad block and there are no bad blocks before the corresponding block in the sequence.

8. The apparatus of claim 1 , wherein:
the circuit comprises a register and an address state machine connected to the register; the register is configured to store addresses of one or more bad blocks in the first block sequence; and
the address state machine is configured to perform the mapping to substitute a next available good block in the first block sequence for each bad block identified by the register.

9. A method, comprising:
receiving a request to perform an operation, the request comprising a selected logical block address in a first sequence of logical block addresses; and
selecting a good block in a sequence of blocks according to a circuit which maps consecutive logical block addresses in the first sequence of logical block addresses to consecutive good blocks in the sequence of blocks, such that each bad block in the sequence is replaced by a next available good block in the sequence; wherein:
the sequence of blocks is arranged in a trimmed die which is among stacked dice;
the stacked dice comprise an untrimmed die;
the trimmed die comprises a number M blocks;
the untrimmed die comprises a number N blocks, where N>M; and
the circuit comprises a register which identifies N-M trimmed physical blocks of the trimmed die as bad blocks.

10. The method of claim 9 , wherein:
a position of each logical block address in the first sequence of logical block addresses corresponds to a position of a block in the sequence; and
the selecting of the of the good block comprises:
determining a block having a position in the sequence corresponding to the position of the selected logical block address in the first sequence of logical block addresses;
determine a number X>1 of bad blocks before, and including, the corresponding block in the sequence;
determine a number Y of bad blocks in the X blocks after the corresponding block in the sequence; and
mapping the selected logical block address to a block which is X+Y blocks after the corresponding block in the sequence, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block after the block which is X+Y blocks after the corresponding block.

11. The method of claim 9 , wherein:
the circuit maps consecutive logical block addresses in the first sequence of logical block addresses, starting from a first logical block address in the first sequence of logical block addresses and continuing to a last logical block address in the first sequence of logical block addresses, to consecutive

Assignees

• Sandisk Technologies Llc

Inventors

• Tran Dat
• Tu Loc
• Periyannan Kirubakaran

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title