Selective skipping of blocks in an SSD

Patent metadata

Field	Value
Publication number	US-9286176-B1
Application number	US-201414156354-A
Country	US
Kind code	B1
Filing date	Jan 15, 2014
Priority date	Nov 8, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A solid state drive (SSD), includes: a plurality of solid state memory devices, each solid state memory device including a plurality of memory blocks arranged in a plurality of planes; a storage; and an SSD controller configured to: write data to memory blocks in a predefined sequence, detect a defective memory block in the plurality of solid state memory devices, mark the detected memory block as defective and store an address of a next non-defective memory block, and in response to data to be written to the marked memory block, the controller skips the marked memory block and writes the data to the next non-marked memory block.

First claim

What is claimed is:

1. A solid state drive (SSD), comprising:
a plurality of solid state memory devices, wherein one of the plurality of solid state memory devices comprises a plurality of memory blocks arranged in a plurality of planes;
a storage; and
an SSD controller configured to:
write data to the plurality of memory blocks in a predefined sequence,
detect a defective memory block in one of the plurality of memory blocks,
mark the detected memory block as defective and store an address of a next non-defective memory block,
in response to data to be written to the marked memory block, skip the marked memory block and write the data to the next non-marked memory block, and
in response to detecting a weak memory block, periodically mark the weak memory block as defective for a predetermined number of write cycles and then clear the mark.

2. The SSD of claim 1 , wherein the storage comprises a block information data structure configured to contain information indicating whether a memory block is defective and the address of the next non-defective memory block.

3. The SSD of claim 1 , wherein in response to detecting that corresponding memory blocks in each of the plurality of planes in one of the plurality of solid state memory devices are defective, the controller is configured to mark the solid state memory device as defective and skip the device during a write operation to the corresponding memory blocks.

4. The SSD of claim 1 , wherein in response to detecting that corresponding memory blocks in less than all of the plurality of planes in one of the plurality of solid state memory devices are defective, the controller is configured to mark the detected memory blocks as defective and skip only the marked memory blocks during a write operation to the solid state memory device.

5. The SSD of claim 1 , wherein the SSD controller is further configured to determine that the weak memory block is weak based on metadata associated with the weak memory block.

6. The SSD of claim 5 , wherein the SSD controller is configured to determine that the weak memory block is weak when a required error correction level is above a predetermined threshold.

7. A method for writing data to a solid state drive (SSD) comprising a plurality of memory devices, the method comprising:
writing data to a plurality of memory blocks in one of the plurality of memory devices in a predefined sequence;
detecting a defective memory block in the plurality of memory blocks;
marking the detected memory block as defective;
storing an address of a next non-defective memory block;
in response to writing data to the marked memory block, skipping the marked memory block and writing the data to the next non-marked memory block; and
in response to detecting a weak memory block, periodically marking the weak memory block as defective for a predetermined number of write cycles and then clearing the mark.

8. The method of claim 7 , further comprising storing, in a block information data structure, information indicating whether a memory block is defective and the address of the next non-defective memory block.

9. The method of claim 7 , further comprising:
in response to detecting that corresponding memory blocks in each of a plurality of planes in one of the plurality of solid state memory devices are defective, marking the solid state memory device as defective and skipping the device during a write operation to the corresponding memory blocks.

10. The method of claim 7 , further comprising:
in response to detecting that corresponding memory blocks in less than all of a plurality of planes in one of the plurality of solid state memory devices are defective, marking the detected memory blocks as defective and skipping only the marked memory blocks during a write operation to the solid state memory device.

11. The method of claim 7 , further comprising determining that the weak memory block is weak based on metadata associated with the weak memory block.

12. The method of claim 11 , wherein determining that a memory block is weak comprises determining that the weak memory block is weak when a required error correction level is above a predetermined threshold.

13. A solid state drive (SSD), comprising:
a plurality of solid state memory devices, wherein one of the solid state memory devices comprises a plurality of memory blocks arranged in a plurality of planes;
a storage; and
an SSD controller configured to:
read data from the plurality of memory blocks in a predefined sequence,
detect a defective memory block in the plurality of memory blocks,
mark the detected memory block as defective and store an address of a next non-defective memory block,
in response to detecting a weak memory block, periodically mark the weak memory block as defective for a predetermined number of write cycles and then clear the mark, and
in response to data to be read from the marked memory block, skip the marked memory block and read the data from the next non-marked memory block.

14. The SSD of claim 13 , wherein the storage comprises a block information data structure configured to contain information indicating whether a memory block is defective and the address of the next non-defective memory block.

15. The SSD of claim 13 , wherein in response to detecting that corresponding memory blocks in each of the plurality of planes in one of the plurality of solid state memory devices are defective, the controller is configured to mark the solid state memory device as defective and skip the device during a read operation to the corresponding memory blocks.

16. The SSD of claim 13 , wherein in response to detecting that corresponding memory blocks in less than all of the plurality of planes in one of the plurality of solid state memory devices are defective, the controller is configured to mark the detected memory blocks as defective and skip only the marked memory blocks during a read operation to the solid state memory device.

17. A method for reading data from a solid state drive (SSD) comprising a plurality of memory devices, the method comprising:
reading data from a plurality of memory blocks in one of the plurality of memory devices in a predefined sequence;
detecting a defective memory block in one of the plurality of memory blocks;
marking the detected memory block as defective;
storing an address of a next non-defective memory block;
in response to detecting a weak memory block, periodically marking the weak memory block as defective for a predetermined number of write cycles and then clearing the mark; and
in response to reading data from the marked memory block, skipping the marked memory block and reading the data from the next non-marked memory block.

18. The method of claim 17 , further comprising storing, in a block information data structure, information indicating whether a memory block is defective and the address of the next non-defective memory block.

19. A method for writing data to a solid state drive (SSD) comprising a plurality of memory devices, the method comprising:
writing data to or reading data from a plurality of memory blocks in one of the plurality of memory devices in a predefined sequence;
detecting a defective memory block in one of a plurality of solid state memory devices;
marking the detected memory block as defective;
storing an address of a next non-defective memory block;
in response to detecting a weak memory block, periodically marking the weak memory block as defective for a predetermined number of write cycles and then

Assignees

• Western Digital Tech Inc
• Skyera Llc

Inventors

• Tomlin Andrew J
• Jones Justin
• Mullendore Rodney N
• Danilak Radoslav

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G11C29/808

  using a flexible replacement scheme · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title