Memory modules and memory packages including graphene layers for thermal management

Patent metadata

Field	Value
Publication number	US-11081565-B2
Application number	US-201916530757-A
Country	US
Kind code	B2
Filing date	Aug 2, 2019
Priority date	Aug 2, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate having an uppermost layer of graphene that comprises a plurality of openings corresponding to and exposing a plurality of substrate pads; and
a memory die disposed over the substrate on the uppermost layer of graphene and having a plurality of electrical connections, each of the plurality of electrical connections in contact with a corresponding one of the plurality of substrate pads,
wherein the uppermost layer of graphene is in contact with the memory die.

2. The apparatus of claim 1 , wherein the uppermost layer of graphene is configured to convey thermal energy away from the memory die.

3. The apparatus of claim 1 , wherein the uppermost layer of graphene is electrically insulated from the plurality of electrical connections.

4. The apparatus of claim 1 , wherein the substrate is a printed circuit board.

5. The apparatus of claim 1 , wherein the uppermost layer of graphene comprises a plurality of monolayers of graphene.

6. The apparatus of claim 1 , wherein the plurality of electrical connections comprises a plurality of solder joints.

7. The apparatus of claim 1 , wherein the plurality of substrate pads is a first plurality of substrate pads, wherein the memory die is a first memory die, wherein the plurality of electrical connections is a first plurality of electrical connections, and wherein the plurality of openings is a first plurality of openings, further comprising:
a second memory die disposed over the substrate and having a second plurality of electrical connections, each of the second plurality of electrical connections in contact with a corresponding one of the second plurality of substrate pads,
wherein the uppermost layer of graphene comprises a second plurality of openings corresponding to and exposing the second plurality of substrate pads.

8. The apparatus of claim 1 , wherein the apparatus is a dual in-line memory module (DIMM) and wherein the memory device is a DRAM device.

9. An apparatus, comprising:
a printed circuit board (PCB) that comprises a layer of graphene, an edge connector and a plurality of electrical pads operably coupled to the edge connector; and
a plurality of memory devices, each of the memory devices comprising a plurality of electrical contacts, each of the electrical contacts operably coupled to a corresponding one of the plurality of electrical pads,
wherein the layer of graphene is in contact with the plurality of memory devices and configured to convey thermal energy away from the memory devices, the layer of graphene including a plurality of openings corresponding to and exposing the plurality of electrical pads of each of the plurality of memory devices.

10. The apparatus of claim 9 , wherein:
the plurality of electrical pads is a first plurality of electrical pads on a first side of the PCB,
the plurality of memory devices is a first plurality of memory devices,
the layer of graphene is a first layer of graphene, and
the printed circuit board includes on a second side of the PCB opposite the first side a second layer of graphene and a second plurality of electrical pads operably coupled to the edge connector,
the apparatus further comprising a second plurality of memory devices, each of the second plurality of memory devices comprising a plurality of electrical contacts, each of the electrical contacts operably connected to a corresponding one of the second plurality of electrical pads,
wherein the second layer of graphene is in contact with the second plurality of memory devices and configured to convey thermal energy away from the second plurality of memory devices, the second layer of graphene including a plurality of openings corresponding to and exposing the second plurality of electrical pads.

11. The apparatus of claim 9 , wherein the layer of graphene is electrically insulated from the plurality of electrical pads and the plurality of electrical contacts of the plurality of memory devices.

12. The apparatus of claim 9 , wherein the layer of graphene comprises a plurality of monolayers of graphene.

13. The apparatus of claim 9 , wherein the plurality of electrical contacts of the plurality of memory devices is operably connected to a corresponding one of the plurality of electrical pads by a solder joint.

14. The apparatus of claim 9 , wherein the layer of graphene is an uppermost layer of the printed circuit board.

15. A semiconductor device package, comprising:
a substrate including a plurality of substrate pads;
a semiconductor die including a plurality of electrical contacts, each one of the plurality of electrical contacts operably coupled to a corresponding one of the plurality of substrate pads; and
a layer of graphene between the substrate and the semiconductor die and in contact with the semiconductor die, the layer of graphene including a plurality of openings corresponding to and exposing the plurality of substrate pads, the layer of graphene configured to convey thermal energy away from the semiconductor die.

16. The semiconductor device package of claim 15 , wherein the semiconductor die comprises one or more memory dies, controller dies, processor dies, or some combination thereof.

17. The semiconductor device package of claim 15 , further comprising a thermal structure in contact with the layer of graphene and configured to export heat from the semiconductor device package.

18. The semiconductor device package of claim 15 , wherein the layer of graphene is electrically insulated from the plurality of electrical contacts and the plurality of substrate pads.

19. The semiconductor device package of claim 15 , wherein the layer of graphene comprises a plurality of monolayers of graphene.

Assignees

• Micron Technology Inc

Inventors

• Yoo Chan H
• Pax George E
• Sharma Yogesh
• King Gregory A
• Kinsley Thomas H
• Richards Randon K

Classifications

• H10W70/695

  Organic materials · CPC title

• H10W70/417

  Bonding materials between chips and die pads · CPC title

• H10W70/413

  Insulating or insulated substrates serving as die pads (H10W70/468 takes precedence) · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W40/10

  Arrangements for heating · CPC title