Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, display device

US11081501B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11081501-B2
Application numberUS-201916395660-A
CountryUS
Kind codeB2
Filing dateApr 26, 2019
Priority dateSep 17, 2018
Publication dateAug 3, 2021
Grant dateAug 3, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a thin film transistor, the method comprising: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, wherein the metal oxide layer at least covers a part of the active layer between the source electrode and the drain electrode, the metal oxide layer extends over and at least covers a surface of each of the source electrode and the drain electrode away from the base substrate, and the source electrode and the drain electrode are spaced apart and insulated from each other by the metal oxide layer. 2. The method according to claim 1 , wherein the processing the metal layer to form the source electrode, the drain electrode, and the metal oxide layer comprises: etching a first portion of the metal layer in a first predetermined region on the active layer by an etching depth, the etching depth being less than a thickness of the metal layer; and performing an oxidation treatment on the metal layer etched to form the source electrode, the drain electrode, and the metal oxide layer, a remaining portion of the metal layer etched in the first predetermined region being completely oxidized. 3. The method according to claim 2 , wherein an orthographic projection of the first predetermined region on the base substrate falls within an orthographic projection of the active layer on the base substrate. 4. The method according to claim 2 , wherein the oxidation treatment is performed by an oxidation depth, the oxidation depth is smaller than the thickness of the metal layer. 5. The method according to claim 4 , wherein the oxidation depth is controlled by adjusting an oxidation parameter. 6. The method according to claim 2 , wherein the etching depth is controlled by an etching duration and/or an etching solution concentration. 7. The method according to claim 2 , wherein the oxidation treatment comprises anodic oxidation and/or thermal oxidation. 8. The method according to claim 2 , wherein the forming the metal layer on the active layer comprises: forming the metal layer on the base substrate on which the active layer is formed such that an orthographic projection of the active layer on the base substrate falls within an orthographic projection of the metal layer on the base substrate. 9. The method according to claim 8 , further comprising: etching a second portion of the metal layer in a second predetermined region and a third portion of the metal layer in a third predetermined region by the etching depth while etching the first portion of the metal layer in the first predetermined region on the active layer, the second predetermined region and the third predetermined region being respectively on opposite sides of the active layer. 10. The method according to claim 9 , wherein the source electrode is formed between the first predetermined region and the second predetermined region, and the drain electrode is formed between the first predetermined region and the third predetermined region. 11. The method according to claim 1 , wherein a material of the metal layer comprises aluminum or an aluminum-neodymium alloy. 12. The method according to claim 1 , wherein the active layer comprises an oxide. 13. The method according to claim 12 , wherein the oxide comprises amorphous IGZO. 14. The method according to claim 1 , wherein before forming an active layer on the base substrate, the method further comprises: forming a gate electrode on the base substrate; and forming a gate insulating layer on the base substrate on which the gate electrode is formed, the gate insulating layer covering the gate electrode, wherein the active layer is formed on a side of the gate insulating layer facing away from the base substrate. 15. The method according to claim 1 , wherein the source electrode covers a first end of the active layer, the drain electrode covers a second end of the active layer, the metal oxide layer further extends over and at least covers a side surface of the source electrode away from the drain electrode, and the metal oxide layer further extends over and at least covers a side surface of the drain electrode away from the source electrode. 16. The method according to claim 1 , wherein a material of the metal oxide layer is made of an oxide of a metal material of which the source electrode and the drain electrode are made.

Assignees

Inventors

Classifications

  • Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

  • by liquid etching only · CPC title

  • Formation by anodic treatments, e.g. anodic oxidation · CPC title

  • of a metallic layer · CPC title

  • composed of oxides, glassy oxides or oxide-based glasses · CPC title

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What does patent US11081501B2 cover?
A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide l…
Who is the assignee on this patent?
Hefei Xinsheng Optoelectronics Technology Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 03 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).