Oxide thin film transistor, manufacturing method thereof, array substrate and display device

US10559698B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10559698-B2
Application numberUS-201815995706-A
CountryUS
Kind codeB2
Filing dateJun 1, 2018
Priority dateSep 22, 2017
Publication dateFeb 11, 2020
Grant dateFeb 11, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the present application provide an Oxide TFT, a manufacturing method thereof, an array substrate and a display device. The Oxide TFT includes a base substrate; a gate electrode, a gate insulating layer and an active layer which are located on the base substrate; a source electrode and a drain electrode, the active layer is at least partly covered with the source electrode and the drain electrode; and a channel protection layer located between the source electrode and the drain electrode, each of the source electrode and the drain electrode includes at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer are stacked one on another, the channel protection layer is of a metal oxide.

First claim

Opening claim text (preview).

What is claimed is: 1. An oxide thin film transistor (Oxide TFT), comprising: a base substrate; a gate electrode, a gate insulating layer and an active layer that are on the base substrate; a source electrode and a drain electrode, the active layer being at least partly covered with the source electrode and the drain electrode; and a channel protection layer between the source electrode and the drain electrode, each of the source electrode and the drain electrode comprising at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer being stacked one on another, wherein a material of the second metallic layer is Copper (Cu), a material of the first metallic layer is configured to be capable of being directly oxidized by an etchant of the second metallic layer, and the channel protection layer is of a metal oxide of at least a part of the first metallic layer. 2. The Oxide TFT according to claim 1 , wherein the channel protection layer is a part of the first metallic layer which is between the source electrode and the drain electrode and has been subjected to an oxidation treatment. 3. The Oxide TFT according to claim 1 , wherein a material of the first metallic layer is aluminum (Al), and a material of the channel protection layer is an aluminum oxide compound. 4. The Oxide TFT according to claim 2 , further comprising a barrier layer, wherein the barrier layer is a part of the first metallic layer in the source electrode and a part of the first metallic layer in the drain electrode which have not been subjected to the oxidation treatment. 5. The Oxide TFT according to claim 1 , further comprising a passivation layer, wherein the source electrode, the drain electrode and the channel protection layer are covered with the passivation layer. 6. An array substrate, comprising an oxide thin film transistor (Oxide TFT), the Oxide TFT comprising: a base substrate; a gate electrode, a gate insulating layer and an active layer that are on the base substrate; a source electrode and a drain electrode, the active layer being at least partly covered with the source electrode and the drain electrode; and a channel protection layer between the source electrode and the drain electrode, each of the source electrode and the drain electrode comprising at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer being stacked one on another, wherein a material of the second metallic layer is Copper (Cu), a material of the first metallic layer is configured to be capable of being directly oxidized by an etchant of the second metallic layer, and the channel protection layer is of a metal oxide of at least a part of the first metallic layer. 7. The array substrate according to claim 6 , wherein the channel protection layer is a part of the first metallic layer which is between the source electrode and the drain electrode and has been subjected to an oxidation treatment. 8. The array substrate according to claim 6 , wherein a material of the first metallic layer is aluminum (Al), and a material of the channel protection layer is an aluminum oxide compound. 9. The array substrate according to claim 7 , further comprising a barrier layer, wherein the barrier layer is a part of the first metallic layer in the source electrode and a part of the first metallic layer in the drain electrode which have not been subjected to the oxidation treatment. 10. The array substrate according to claim 6 , further comprising a passivation layer, wherein the source electrode, the drain electrode and the channel protection layer are covered with the passivation layer.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10559698B2 cover?
Embodiments of the present application provide an Oxide TFT, a manufacturing method thereof, an array substrate and a display device. The Oxide TFT includes a base substrate; a gate electrode, a gate insulating layer and an active layer which are located on the base substrate; a source electrode and a drain electrode, the active layer is at least partly covered with the source electrode and the…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Fuzhou Boe Optoelectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L29/7869. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 11 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).