Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask

Patent metadata

Field	Value
Publication number	US-11081387-B2
Application number	US-201916713044-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Sep 25, 2017
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer;
patterning the photoresist layer to form a via mask, wherein the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer;
etching the film layer and the dielectric layer based on the patterned photoresist layer;
ashing the photoresist layer and the film layer;
etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region;
etching the hard mask layer and the dielectric layer; and
performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

2. The method of claim 1 , wherein the dielectric layer includes a plurality of dielectric layers including a capped layer.

3. The method of claim 1 , further comprising:
forming a stack including the dielectric layer and the hard mask layer,
wherein the film layer is a first film layer and the photoresist layer is a first photoresist layer, and
wherein the stack includes a second film layer and a second photoresist layer;
patterning the first photoresist layer and, based on the patterned first photoresist layer, etching the hard mask layer to form the metal line mask in the hard mask layer;
ashing the first photoresist layer and the first film layer; and
forming the second film layer and the second photoresist layer on the hard mask layer.

4. The method of claim 3 , wherein the second film layer comprises at least one of amorphous silicon or an anti-reflective coating film.

5. The method of claim 1 , wherein:
the hard mask layer is formed on the dielectric layer;
the film layer is formed on the hard mask layer; and
the photoresist layer is formed on the film layer.

6. The method of claim 1 , wherein the hard mask layer is formed of titanium nitride.

7. The method of claim 1 , wherein:
the hard mask layer is used as a first mask layer to mask a portion of the dielectric layer; and
the portion of the dielectric layer is used as a second mask layer to mask a second portion of the dielectric layer.

8. The method of claim 1 , wherein the film layer comprises at least one of amorphous silicon or an anti-reflective coating film.

9. The method of claim 1 , wherein the film layer and the dielectric layer are anisotropically etched based on the patterned photoresist layer.

10. The method of claim 1 , wherein the etching of the dielectric layer comprises etching a first portion of the dielectric layer based on a pattern of the hard mask layer and a pattern of a second portion of the dielectric layer.

11. The method of claim 1 , wherein the dielectric layer is anisotropically etched based on the pattern of the hard mask layer.

12. The method of claim 1 , further comprising, prior to forming the dielectric layer, forming an interconnect layer and forming an etch stop layer on the interconnect layer,
wherein subsequent to etching the dielectric layer and prior to performing the plurality of dual damascene process operations, etching the etch stop layer until a top surface of the interconnect layer is reached.

13. The method of claim 1 , wherein the plurality of dual damascene process operations comprise:
forming a barrier layer in the via region and the metal line region;
forming a seed layer on the barrier layer; and
electroplating the seed layer.

14. A processing system for processing a substrate and forming an integrated circuit, wherein the processing system comprises:
a processor;
a memory; and
one or more applications stored in the memory and including instructions, which are executable by the processor to
form a dielectric layer, a hard mask layer, a film layer and a photoresist layer;
pattern the photoresist layer to form a via mask, wherein the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer;
etch the film layer and the dielectric layer based on the patterned photoresist layer;
ash the photoresist layer and the film layer;
etch the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region;
etch the hard mask layer and the dielectric layer; and
perform a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

15. The processing system of claim 14 , wherein the instructions are executable by the processor to:
form a stack including the dielectric layer and the hard mask layer,
wherein the film layer is a first film layer and the photoresist layer is a first photoresist layer, and
wherein the stack includes a second film layer and a second photoresist layer;
pattern the first photoresist layer and, based on the patterned first photoresist layer, etch the hard mask layer to form the metal line mask in the hard mask layer;
ash the first photoresist layer and the first film layer; and
form the second film layer and the second photoresist layer on the hard mask layer.

16. The processing system of claim 14 , wherein:
the hard mask layer is used as a first mask layer to mask a first portion of the dielectric layer; and
the first portion of the dielectric layer is used as a second mask layer to mask a second portion of the dielectric layer.

17. The processing system of claim 14 , wherein:
the film layer is formed on the hard mask layer; and
the photoresist layer is formed on the film layer.

18. The processing system of claim 14 , wherein:
the film layer and the dielectric layer are anisotropically etched based on the patterned photoresist layer; and
the dielectric layer is anisotropically etched based on the pattern of the hard mask layer.

19. The processing system of claim 14 , wherein the etching of the dielectric layer comprises:
etching a first portion of the dielectric layer based on a pattern of the hard mask layer and a pattern of a second portion of the dielectric layer;
subsequent to etching the first portion of the dielectric layer, etching the second portion of the dielectric layer based on a pattern of the hard mask layer; and
subsequent to etching the second portion of the dielectric layer, etching the first portion of the dielectric layer based on a pattern of the hard mask layer and a pattern of the second portion of the dielectric layer.

20. The processing system of claim 14 , wherein the plurality of dual damascene process operations comprise:
forming a barrier layer in the via region and the metal line region;
forming a seed layer on the barrier layer; and
electroplating the seed layer.

Assignees

• Marvell World Trade Ltd
• Marvell Asia Pte Ltd

Inventors

• Chang Runzi
• She Min

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title