Method for stabilizing a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-11081384-B2
Application number	US-201916388632-A
Country	US
Kind code	B2
Filing date	Apr 18, 2019
Priority date	Apr 19, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A method includes producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion. The method further includes permanently securing a first carrier to the first surface of the semiconductor arrangement.

First claim

What is claimed is:

1. A method, comprising:
producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion;
permanently securing a first carrier to the first surface of the semiconductor arrangement;
before permanently securing the first carrier to the first surface of the semiconductor arrangement, securing a second carrier to a second surface of the semiconductor arrangement, the second surface facing away from the first surface; and
after permanently securing the first carrier to the first surface of the semiconductor arrangement, removing the second carrier from the second surface.

2. The method of claim 1 , wherein permanently securing the first carrier to the first surface of the semiconductor arrangement comprises:
contacting a first surface of the first carrier with the first insulation layer; and
carrying out a thermal process at temperatures of less than 350° C.

3. The method of claim 2 , wherein the first carrier comprises an insulation layer at least along the first surface of the first carrier.

4. The method of claim 3 , wherein the insulation layer of the first carrier is of a same type as the first insulation layer of the semiconductor arrangement.

5. The method of claim 2 , wherein the first carrier comprises a layer composed of a material selected from the group consisting of:
a semiconductor material;
a metal; and
a glass.

6. The method of claim 2 , wherein the first insulation layer is an oxide layer, and wherein the first carrier consists of a semiconductor material.

7. The method of claim 1 , wherein permanently securing the first carrier to the first surface of the semiconductor arrangement comprises:
adhesively bonding the first carrier onto the first surface of the semiconductor arrangement by an adhesive layer.

8. The method of claim 7 , wherein the adhesive layer comprises benzocyclobutene.

9. The method of claim 1 , wherein permanently securing the first carrier to the first surface of the semiconductor arrangement comprises:
adhesively bonding the first carrier onto the first surface of the semiconductor arrangement by a solder layer.

10. The method of claim 1 , wherein the first surface of the semiconductor arrangement is formed by the insulation layer.

11. The method of claim 1 , wherein the semiconductor arrangement further comprises a metallization on the first insulation layer, and wherein the metallization forms the first surface of the semiconductor arrangement.

12. The method of claim 1 , wherein the semiconductor arrangement comprises a second insulation layer arranged between the semiconductor layer and the second surface.

13. The method of claim 12 , wherein at least one semiconductor component is integrated in the region of the semiconductor layer which is surrounded by the via in a ring-shaped fashion, and wherein a wiring structure is arranged in the first insulation layer, the wiring structure contacting the at least one semiconductor component.

14. The method of claim 1 , wherein producing the semiconductor arrangement comprises:
forming the via such that the via ends in the semiconductor layer;
reducing a thickness of the semiconductor layer such that the via is exposed at a first surface of the semiconductor layer;
producing the first insulation layer on the first surface of the semiconductor layer,
wherein before reducing the thickness of the semiconductor layer, the second carrier is secured to the second surface of the semiconductor arrangement.

15. The method of claim 1 , wherein the semiconductor arrangement is part of a wafer comprising a multiplicity of semiconductor arrangements, wherein the first carrier is applied simultaneously on respective first surfaces of the multiplicity of semiconductor arrangements to form a wafer arrangement, and wherein the wafer arrangement is divided.

16. The method of claim 1 , further comprising:
securing the first carrier to an additional carrier after the first carrier is permanently secured to the first surface of the semiconductor arrangement.

17. The method of claim 16 , wherein the additional carrier is a leadframe.

18. The method of claim 1 , further comprising:
reducing a thickness of the first carrier proceeding from a surface facing away from the semiconductor arrangement after permanently securing the first carrier to the first surface of the semiconductor arrangement.

19. The method of claim 1 , further comprising:
integrating a semiconductor component and/or a semiconductor circuit in the region of the semiconductor layer surrounded by the insulating via in the ring-shaped fashion.

20. The method of claim 19 , wherein integrating a semiconductor component and/or a semiconductor circuit in the region of the semiconductor layer surrounded by the insulating via in the ring-shaped fashion comprises:
integrating a lateral power transistor in the region of the semiconductor layer surrounded by the insulating via in the ring-shaped fashion.

Assignees

• Infineon Technologies Ag

Inventors

• Gruber Hermann
• Busch Joerg

Classifications

• H10W72/07355

  changes in materials · CPC title

• H10W72/351

  Materials of die-attach connectors · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/456

  Materials · CPC title

• H10W20/48

  Insulating materials thereof · CPC title