Multiple back gate transistor

Patent metadata

Field	Value
Publication number	US-9761525-B1
Application number	US-201615142525-A
Country	US
Kind code	B1
Filing date	Apr 29, 2016
Priority date	Apr 29, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

First claim

What is claimed:

1. A structure, comprising:
a transistor formed over a semiconductor material and an underlying substrate; and
multiple isolated contact regions under a body of the transistor in at least a channel and under source and drain regions of the transistor, which are structured to provide a local potential to the body or the channel of the transistor at different locations,
wherein the isolated contact regions are conductive contacts in a wafer, separated from the transistor by the oxide layer and the semiconductor layer.

2. The structure of claim 1 , wherein the isolated contact regions are separated laterally by insulating material.

3. The structure of claim 1 , wherein the isolated contact regions are separated laterally by doping of an opposite type than that of the multiple isolated contact regions.

4. The structure of claim 1 , wherein the local potential at the different locations are different potentials applied to different regions of the transistor.

5. The structure of claim 1 , wherein the isolated contact regions are along a length of the transistor.

6. The structure of claim 1 , wherein the isolated contact regions are along a width of the transistor.

7. The structure of claim 1 , wherein the isolated contact regions are conductive contacts in an oxide layer, underlying the semiconductor material.

8. The structure of claim 7 , wherein the conductive contacts extend entirely through the oxide layer, contacting the semiconductor material and wires formed under the oxide layer, with an adhesive layer bonding the underlying substrate to the oxide layer.

9. The structure of claim 7 , wherein the conductive contacts extend partially through the oxide layer, leaving a space between an end of the conductive contacts and the semiconductor material.

10. The structure of claim 1 , wherein the conductive contacts are formed partially through the wafer.

11. The structure of claim 1 , wherein the conductive contacts are a first dopant type and the wafer is a second dopant type, opposite the first dopant type.

12. A structure, comprising:
a transistor; and
multiple backside conductive contacts under the transistor which provide different biases at different locations to a body of the transistor.

13. The structure of claim 12 , wherein the multiple backside conductive contacts are separated laterally by insulating material.

14. The structure of claim 12 , wherein the multiple backside conductive contacts are separated laterally by doping of an opposite type than that of the multiple backside contacts.

15. The structure of claim 12 , wherein:
the multiple backside conductive contacts are along a length of the transistor or a width of the transistor located in a channel region and under source and drain regions of the transistor; and
the multiple backside conductive contacts are formed entirely through an insulator layer and contact a semiconductor layer in which portions of the transistor are formed directly thereon.

16. The structure of claim 12 , wherein the multiple backside conductive contacts are in a buried oxide layer, directly contacting semiconductor material on which the transistor is formed.

17. The structure of claim 12 , wherein the multiple backside conductive contacts are in a buried oxide layer, separated from a bottom surface of semiconductor material on which the transistor is formed.

18. The structure of claim 12 , wherein the multiple backside conductive contacts are formed in a wafer, separated from semiconductor material by an insulating material.

19. A structure, comprising:
a transistor provided on a wafer;
a first backside conductive region under a first edge of the transistor;
a second backside conductive region extending under a second edge of the transistor;
one or more multiple backside conductive regions under a channel region of the transistor; and
a voltage bias connecting to each of the first, second and one or more multiple backside conductive regions from a front side of the wafer, which provide different biases at different locations to a body of the transistor.

Assignees

• Globalfoundries Inc

Inventors

• Hook Terence B
• Phelps Richard A
• Stamper Anthony K
• Camillo-Castillo Renata A

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title