Memory plane structure for ultra-low read latency applications in non-volatile memories

Patent metadata

Field	Value
Publication number	US-11081192-B2
Application number	US-201916668949-A
Country	US
Kind code	B2
Filing date	Oct 30, 2019
Priority date	Oct 30, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

First claim

What is claimed is:

1. A memory device, comprising:
a semiconductor substrate in which a memory cell region and a peripheral region are defined, the memory cell region comprising a plurality of co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate, wherein each memory cell plane is comprised of:
a plurality of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate, wherein each sub-plane comprises an (n)-bit programmable memory cell array having an (n)-number of bit lines;
a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the plurality of sub-planes such that, adjacent to each sub-plane is a sense amplifier region wherein, apart from the sense amplifier regions positioned at terminating ends of the memory cell plane, each sense amplifier region is operable with respect to at least a fraction of the (n)-number of bit lines of the two sub-planes immediately adjacent to the sense amplifier region; and
wherein each bit line only traverses one sub-plane and one sense amplifier region.

2. The memory device according to claim 1 , wherein the memory cell array comprises non-volatile memory cells.

3. The memory device according to claim 1 , further comprising a controller communicating with the memory cell region.

4. The memory device according to claim 1 , wherein the fraction is equal to one half of (n)-number.

5. The memory device according to claim 1 , wherein the memory cell region comprises sixteen memory cell planes, each memory cell plane comprising:
eight sub-planes; and
nine sense amplifier regions.

6. The memory device according to claim 5 , wherein a bit line length of each bit line is approximately 2 KB.

7. The memory device according to claim 6 , wherein a read latency performance of the memory cell region is one of:
one microsecond; or
below one microsecond.

8. The memory device according to claim 1 , wherein:
each of the sub-planes is equal in length along the axis;
each of the sense amplifier regions is equal in length along the axis; and
a length of each sub-plane along the axis is greater than a length of each sense amplifier region along the axis.

9. The memory device according to claim 1 , wherein:
a length of each bit line traverses its respective sub-plane and sense amplifier region; and
the portion of the bit line length that traverses the sub-plane is greater than the portion of the bit line length that traverses the sense amplifier region.

10. A memory device, comprising:
a semiconductor substrate in which a memory cell region and a peripheral region are defined, the memory cell region comprising a plurality of co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate, wherein each memory cell plane is comprised of:
an (m)-number of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate, wherein each sub-plane comprises an (n)-bit programmable memory cell array having an (n)-number of bit lines;
an (m+1) number of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that, adjacent to each sub-plane is a sense amplifier region wherein, apart from the sense amplifier regions positioned at terminating ends of the memory cell plane, each sense amplifier region is operable with respect to at least a fraction of the (n)-number of bit lines of the two sub-planes immediately adjacent to the sense amplifier region; and

wherein each bit line only traverses one sub-plane and one sense amplifier region.

11. The memory device according to claim 10 , wherein the memory cell array comprises non-volatile memory cells.

12. The memory device according to claim 10 , further comprising a controller communicating with the memory cell region.

13. The memory device according to claim 10 , wherein the fraction is equal to one half of (n)-number.

14. The memory device according to claim 10 , wherein the memory cell region comprises sixteen memory cell planes and (m) equals eight.

15. The memory device according to claim 14 , wherein a bit line length of each bit line is approximately 2 KB.

16. The memory device according to claim 15 , wherein a read latency performance of the memory cell region is one of:
one microsecond; or
below one microsecond.

17. The memory device according to claim 10 , wherein:
each of the sub-planes is equal in length along the axis;
each of the sense amplifier regions is equal in length along the axis; and
a length of each sub-plane along the axis is greater than a length of each sense amplifier region along the axis.

18. The memory device according to claim 10 , wherein:
a length of each bit line traverses its respective sub-plane and sense amplifier region; and
the portion of the bit line length that traverses the sub-plane is greater than the portion of the bit line length that traverses the sense amplifier region.

19. A method for reducing the bit line capacitance in a non-volatile memory device, comprising:
in a memory device having a semiconductor substrate in which a memory cell region and a peripheral region are defined, partitioning the memory cell region into a plurality of co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate;
partitioning each memory cell plane into a plurality of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate, wherein each sub-plane comprises an (n)-bit programmable memory cell array having an (n)-number of bit lines; and
arranging a plurality of sense amplifier regions along the axis in an alternating pattern with the plurality of sub-planes such that, adjacent to each sub-plane is a sense amplifier region wherein, apart from the sense amplifier regions positioned at terminating ends of the memory cell plane, each sense amplifier region is operable with respect to at least a fraction of the (n)-number of bit lines of the two sub-planes immediately adjacent to the sense amplifier region; and
wherein each bit line only traverses one sub-plane and one sense amplifier region.

20. The method according to claim 19 , wherein:
a length of each bit line traverses its respective sub-plane and sense amplifier region; and
the portion of the bit line length that traverses the sub-plane is greater than the portion of the bit line length that traverses the sense amplifier region.

Assignees

• Sandisk Technologies Llc
• SanDiskTechnologies LLC

Inventors

• Yabe Hiroki
• Hayashi Koichiro
• Ariki Takuya
• Fujita Yuki
• Ookuma Naoki
• Yamauchi Kazuki
• Takehara Masahito
• Miwa Toru

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title