Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods

Patent metadata

Field	Value
Publication number	US-10153007-B2
Application number	US-201514944622-A
Country	US
Kind code	B2
Filing date	Nov 18, 2015
Priority date	May 24, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

First claim

What is claimed is:

1. An apparatus, comprising:
a local input/output configured to be coupled to a sense amplifier, the local input/output line being a differential pair of signal lines;
a global read line, the global read line being a differential pair of signal lines;
a global write line; the global write line being a differential pair of signal lines; and
a local read/write circuit coupled to the local input/output line, the global read line, and the global write line, the local read/write circuit configured to:
provide a voltage difference from the local input/output line, to the global read line, responsive to a read operation, and
provide a voltage difference from the global write line to the local input/output line responsive to a write operation,

the local read/write circuit comprising a read circuit directly coupled to the local input/output line and the global read line but not to the global write line,
the local read/write circuit further comprising a write circuit directly coupled to the local input/output line and the global write line but not to the global read line,
the local read/write circuit further comprising a precharge circuit coupled to the local input/output line, the precharge circuit configured to control the read circuit during precharge by precharging local input/output line to a precharge voltage.

2. The apparatus of claim 1 wherein the read circuit is coupled to the local input/output line and configured to couple a signal line of the global read line to a read voltage based at least in part on the voltage difference on the local input/output line, and
wherein the write circuit is coupled to the local input/output line and configured to couple the global write line to the local input/output line responsive to being activated to provide the voltage difference to the local input/output line.

3. The apparatus of claim 2 wherein the precharge circuit comprises: a pair of precharge switches coupled to the local input/output line and configured to be coupled to the precharge voltage, and
wherein the pair of precharge switches are configured to couple the local input/output line to the precharge voltage responsive to being activated.

4. The apparatus of claim 3 wherein the pair of precharge switches comprise a pair of p-channel field effect transistors (PFETs) coupled to the local input/output line and a supply voltage.

5. The apparatus of claim 3 wherein the pair of precharge switches comprise a pair of n-channel field effect transistors (NFETs) coupled to the local input/output line and ground.

6. The apparatus of claim 2 wherein the precharge voltage is a high voltage level.

7. The apparatus of claim 2 wherein the precharge voltage is a low voltage level.

8. The apparatus of claim 2 wherein the read circuit comprises:
a first read switch coupled to a first signal line of the global read line and including a first gate coupled to a first signal line of the local input/output line; and
a second read switch coupled to a second signal line of the global read line and including a second gate coupled to a second signal line of the local input/output line, the first and second read switches configured to be coupled to the read voltage.

9. The apparatus of claim 2 wherein the write circuit comprises:
a first write switch coupled to a first signal line of the global write line and further coupled to a first signal line of the local input/output line; and
a second write switch coupled to a second signal line of the global write line and further coupled to a second signal line of the local input/output line.

10. The apparatus of claim 4 , further comprising:
a wordline extending in a direction perpendicular to the global read line and the global write line; and
a column select line extending in a same direction as the wordline.

11. An apparatus, comprising:
a sense amplifier configured to provide a voltage difference;
a first pair of signal lines;
a column select line in a sense amplifier region among a plurality of sense amplifier regions alternately disposed with a plurality of memory sections;
a column select circuit coupled to the sense amplifier and the first pair of signal lines, the column select circuit configured to be activated by the column select line disposed in the sense amplifier region to couple the sense amplifier to the first pair of signal lines to provide the voltage difference to the first pair of signal lines;
a second pair of signal lines;
a third pair of signal lines;
a local read/write circuit coupled to the first, second, and third pairs of signal lines; and
a wordline included in a memory section of the plurality of memory sections adjacent to the sense amplifier region including the column select line,
wherein the column select line included in the sense amplifier region extends in a direction parallel to the wordline included in the memory section.

12. The apparatus of claim 11 , wherein the column select line extending in a direction parallel to the wordline is used to provide a column select signal, via at least one line different from the column select line, to at least one respective column select switch in a column select circuit of the sense amplifier region.

13. The apparatus of claim 12 , further comprising:
a column decoder coupled to the column select line,
wherein the at least one line is configured to provide the column select signal from the column decoder to the least one respective column select switch in the column select circuit of the sense amplifier region.

14. The apparatus of claim 11 wherein the column select circuit comprises:
a first column select switch coupled to a first signal line of the first pair of signal lines; and
a second column select switch coupled to a second signal line of the first pair of signal lines, the first and second column select switches configured to couple the first and second signal lines of the first pair of signal lines to the sense amplifier responsive to being activated.

15. The apparatus of claim 11 wherein the local read/write circuit comprises:
a read circuit coupled to the first pair of signal lines and configured to couple a signal line of the second pair of signal lines to a read voltage based at least in part on the voltage difference on the first pair of signal lines; and
a write circuit coupled to the first pair of signal lines and configured to couple the third pair of signal lines to the first pair of signal lines responsive to being activated to provide the voltage difference to the first pair of signal lines.

16. The apparatus of claim 11 wherein the first pair of signal lines comprises a differential pair of local input/output lines.

17. The apparatus of claim 11 wherein the second pair of signal lines comprises a differential pair of global read lines and the third pair of signal lines comprises a different pair of global write lines.

18. The apparatus of claim 11 wherein the sense amplifier is configured to be coupled to a differential pair of digit lines.

19. An apparatus, comprising:
a sense amplifier configured to amplify a voltage difference between a pair of digit lines and output a read voltage based on the voltage difference;
a local input/output line coupled to the sense amplifier and configured to receive the read voltage;
a global read line;
a global write line provided independently of the global read line;
a local read/write circuit coupled to the local input/output line, the global read line, and the global write line;
a wordline; and
a colu

Assignees

• Micron Technology Inc

Inventors

• Venkata Harish N
• Schreck John F
• Fardad Mansour

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C7/062 Primary

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title