Memory device random option inversion

Patent metadata

Field	Value
Publication number	US-11081166-B1
Application number	US-202017000202-A
Country	US
Kind code	B1
Filing date	Aug 21, 2020
Priority date	Aug 21, 2020
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.

First claim

What is claimed is:

1. An apparatus, comprising:
a first set of fuses configured to output a first set of logic states associated with configuration of a memory device;
first circuitry coupled with the first set of fuses and configured to sequence the first set of logic states over a plurality of phases of a set of lanes;
a second set of fuses configured to output a second set of logic states;
second circuitry configured to decode one or more phases and one or more lanes based at least in part on the second set of logic states;
third circuitry configured to select between a respective logic state and a respective inverted logic state for the one or more phases of the one or more lanes based at least in part on the one or more lanes and the one or more phases; and
a set of latches configured to store the respective logic states or the respective inverted logic states based at least in part on the selection.

2. The apparatus of claim 1 , wherein the second set of fuses comprises a plurality of groups of fuses, each group of fuses comprising a first subset of fuses associated with a phase of the plurality of phases and a second subset of fuses associated with a lane of the one or more lanes.

3. The apparatus of claim 2 , wherein:
the plurality of phases are grouped in a plurality of cycles of the set of lanes;
each group of fuses of the second set of fuses further comprises a third subset of fuses associated with a cycle of the plurality of cycles;
the first circuitry is further configured to sequence the first set of logic states over the plurality of cycles of the set of lanes; and
the second circuitry is further configured to decode one or more cycles based at least in part on the second set of logic states.

4. The apparatus of claim 2 , wherein the second circuitry comprises a plurality of second circuitry blocks associated with each group of the plurality of groups of fuses of the second set of fuses, each of the plurality of second circuitry blocks being configured to compare the sequenced plurality of phases to the phase of each group of fuses.

5. The apparatus of claim 2 , wherein the second subset of fuses of each group of fuses of the second set of fuses comprises an encoded value for the lane of the one or more lanes.

6. The apparatus of claim 2 , wherein the second subset of fuses of each group of fuses of the second set of fuses comprises a bitmap comprising a plurality of fuses corresponding to the set of lanes.

7. The apparatus of claim 1 , wherein the third circuitry comprises lane inversion logic coupled with the one or more lanes, the lane inversion logic configured to generate the respective inverted logic states for the one or more phases of the one or more lanes.

8. The apparatus of claim 7 , wherein the lane inversion logic comprises one or more multiplexers coupled with the set of latches, the one or more multiplexers configured to output the respective logic states or the generated respective inverted logic states based at least in part on the selection.

9. A method, comprising:
determining a first set of logic states output by a first set of fuses, the first set of logic states associated with configuration of a memory device;
sequencing the first set of logic states over a plurality of phases of a set of lanes;
determining a second set of logic states output by a second set of fuses;
decoding one or more phases and one or more lanes based at least in part on the second set of logic states;
selecting between a respective logic state and a respective inverted logic state for the plurality of phases of the one or more lanes based at least in part on the one or more lanes and the one or more phases; and
storing the respective logic states or the respective inverted logic states based at least in part on the selecting.

10. The method of claim 9 , wherein the second set of fuses comprises a plurality of groups of fuses, each group of fuses comprising a first subset of fuses associated with a phase of the plurality of phases and a second subset of fuses associated with a lane of the one or more lanes.

11. The method of claim 10 , wherein the plurality of phases are grouped in a plurality of cycles of the set of lanes, the method further comprising:
sequencing the first set of logic states over the plurality of cycles of the set of lanes; and
decoding one or more cycles based at least in part on the second set of logic states.

12. The method of claim 10 , wherein the decoding further comprises:
comparing the sequenced plurality of phases to the phase of each group of fuses of the second set of fuses.

13. The method of claim 9 , further comprising:
generating, using lane inversion logic, the respective inverted logic states for the one or more phases of the one or more lanes.

14. The method of claim 13 , further comprising:
outputting, using one or more multiplexers, the respective logic states or the generated respective inverted logic states to one or more latches based at least in part on the selecting, wherein storing the respective logic states or the respective inverted logic states is further based at least in part on the outputting.

15. An apparatus, comprising:
a first set of fuses,
a second set of fuses, and
a controller coupled with the first set of fuses and the second set of fuses, wherein the controller is operable to:
determine a first set of logic states output by the first set of fuses, the first set of logic states associated with configuration of a memory device;
sequence the first set of logic states over a plurality of phases of a set of lanes;
determine a second set of logic states output by the second set of fuses;
decode one or more phases and one or more lanes based at least in part on the second set of logic states;
select between a respective logic state and a respective inverted logic state for the plurality of phases of the one or more lanes based at least in part on the one or more lanes and the one or more phases; and
store the respective logic states or the respective inverted logic states based at least in part on the selecting.

16. The apparatus of claim 15 , wherein the second set of fuses comprises a plurality of groups of fuses, each group of fuses comprising a first subset of fuses associated with a phase of the plurality of phases and a second subset of fuses associated with a lane of the one or more lanes.

17. The apparatus of claim 16 , wherein:
the plurality of phases are grouped in a plurality of cycles of the set of lanes; and
the controller is further operable to:
sequence the first set of logic states over the plurality of cycles of the set of lanes; and
decode one or more cycles based at least in part on the second set of logic states.

18. The apparatus of claim 16 , wherein the controller is further operable to:
compare the sequenced plurality of phases to the phase of each group of fuses of the second set of fuses.

19. The apparatus of claim 15 , wherein the controller is further operable to:
generate the respective inverted logic states for the one or more phases of the one or more lanes.

20. The apparatus of claim 19 , wherein the controller is further operable to:
output the respective logic states or the generated respective inverted logic states to one or more latches based at least in part on the selecting, wherein storing the respective logic states or the respective inverted logic states is further based at least in part on the outputting.

Assignees

• Micron Technology Inc

Inventors

• Werhane Kevin G
• Johnson Jason M
• Fujiwara Yoshinori
• Jensen Tyrel Z
• Miller Daniel S
• Jefferson David E
• Kotti Vivek

Classifications

• G11C29/027

  in fuses · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G11C29/024 Primary

  in decoders · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title