Semiconductor device and imaging device

Patent metadata

Field	Value
Publication number	US-11069735-B2
Application number	US-202016917397-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	May 18, 2015
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.

First claim

The invention claimed is:

1. A light detecting device, comprising:
a first substrate including a plurality of pixels in a pixel array and a first wiring layer, wherein the first wiring layer includes a first electrode and a second electrode; and
a second substrate including a signal processing region and a second wiring layer,
wherein the plurality of pixels outputs a plurality of pixel signals to the signal processing region,
wherein the second wiring layer includes a third electrode and a fourth electrode,
wherein the first electrode is bonded to the third electrode,
wherein the first electrode and the third electrode are electrically connected to each other,
wherein the first electrode is electrically connected to the first substrate,
wherein the third electrode is electrically connected to the second substrate,
wherein the second electrode and the fourth electrode are disposed outside of the pixel array,
wherein the second electrode is bonded to the fourth electrode,
wherein the second electrode and the fourth electrode are electrically connected to a potential that is different from the plurality of pixel signals,
wherein the second electrode and the fourth electrode each includes a plurality of cascading portions provided around perimeters of respective first and second wiring layers, and
wherein one of the cascading portions of each of the plurality of cascading portions provided around perimeters of the respective first and second wiring layers borders end portions of the respective first and second wiring layers.

2. The light detecting device of claim 1 , wherein the first substrate further includes a first via.

3. The light detecting device of claim 2 , wherein the first via is electrically connected to the second electrode.

4. The light detecting device of claim 3 , wherein the second electrode is electrically connected to a grounding conductor.

5. The light detecting device of claim 1 , wherein the first substrate is mechanically bonded to the second substrate.

6. The light detecting device of claim 1 , wherein the signal processing region is configured to perform processing of the pixel signals.

7. The light detecting device of claim 6 , wherein the processing includes analog to digital conversion of the pixel signals.

8. The light detecting device of claim 6 , wherein the signal processing region is configured to generate control signals for the pixels.

9. The light detecting device of claim 1 , wherein the second electrode is a linear metal layer arranged on an outside of the first electrode.

10. The light detecting device of claim 9 , wherein the fourth electrode is a linear metal layer arranged on an outside of the third electrode.

11. The light detecting device of claim 10 , wherein the second electrode, the first electrode, the fourth electrode, and the third electrode are formed from copper.

12. The light detecting device of claim 1 , wherein the first substrate further includes a first insulating layer, wherein the second electrode, the first electrode, and the first insulating layer form portions of a bonding surface of the first substrate.

13. The light detecting device of claim 12 , wherein the second substrate further includes a second insulating layer, wherein the fourth electrode, the third electrode, and the second insulating layer form portions of a bonding surface of the second substrate.

14. The light detecting device of claim 13 , wherein the bonding surface of the first substrate and the bonding surface of the second substrate are bonded together.

15. The light detecting device of claim 14 , wherein the first electrode is embedded in the first insulating layer, and wherein the third electrode is embedded in the second insulating layer.

16. The light detecting device of claim 15 , wherein at least a portion of the first insulating layer between the first electrode and the second electrode and at least a portion of the second insulating layer between the third electrode and the fourth electrode are bonded together.

17. The light detecting device of claim 1 , wherein the second electrode and the fourth electrode have a same width.

18. The light detecting device of claim 1 , wherein the first substrate includes a plurality of wiring layers.

19. The light detecting device of claim 18 , wherein a plurality of vias and the plurality of wiring layers connect the pixels to the processing region.

20. An imaging device, comprising:
a light detecting device, including:
a first substrate including a plurality of pixels in a pixel array and a first wiring layer, wherein the first wiring layer includes a first electrode and a second electrode;
a second substrate including a signal processing region and a second wiring layer,
wherein the plurality of pixels outputs a plurality of pixel signals to the signal processing region,
wherein the second wiring layer includes a third electrode and a fourth electrode,
wherein the first electrode is bonded to the third electrode,
wherein the first electrode and the third electrode are electrically connected to each other,
wherein the first electrode is electrically connected to the first substrate,
wherein the third electrode is electrically connected to the second substrate,
wherein the second electrode and the fourth electrode are disposed outside of the pixel array,
wherein the second electrode is bonded to the fourth electrode,
wherein the second electrode and the fourth electrode are electrically connected to a potential that is different from the plurality of pixel signals,
wherein the second electrode and the fourth electrode each includes a plurality of cascading portions provided around perimeters of respective first and second wiring layers, and
wherein one of the cascading portions of each of the plurality of cascading portions provided around perimeters of the respective first and second wiring layers borders end portions of the respective first and second wiring layers;
a plurality of microlenses, wherein at least one microlens is provided for each pixel in the plurality of pixels; and
a plurality of color filters, wherein the color filters are between the microlenses and the pixels.

Assignees

• Sony Corp

Inventors

• Kotoo Kengo
• Koike Kaoru

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title