Semiconductor memory element, other elements, and their production methods

Patent metadata

Field	Value
Publication number	US-11069713-B2
Application number	US-201716315784-A
Country	US
Kind code	B2
Filing date	Jul 3, 2017
Priority date	Jul 6, 2016
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.

First claim

What is claimed is:

1. A semiconductor memory element, comprising:
a semiconductor substrate having a source region and a drain region;
a buffer insulator formed on the semiconductor substrate;
a stacked ferroelectric formed on the buffer insulator;
a stacked conductor formed on the stacked ferroelectric; and
a partition wall surrounding a side surface of the stacked ferroelectric,
wherein a cross-sectional area of the stacked ferroelectric parallel with the semiconductor substrate is narrowest at a bottom surface of the stacked ferroelectric, a length (L) between the source region and the drain region being equal to or smaller than 100 nm,
a distance (H) between the stacked conductor and the bottom surface of the stacked ferroelectric is equal to or greater than double the length (L),
the semiconductor memory element has an intensity of the memory function that becomes stronger as L decreases in a range of L≤(2×k×d) and that disappears when L>(2×k×d),
where d: a controlled film thickness of the stacked ferroelectric which is measured on a flat surface, and
k: a ratio of ferroelectric film-forming speed on an inner wall surface and a horizontal surface of a groove defined by the partition wall, where 0<k≤1.

2. The semiconductor memory element according to claim 1 ,
wherein an area of cross section parallel to the semiconductor substrate of said ferroelectric does not decrease with increase of the distance of said cross section from a bottom surface of said ferroelectric.

3. The semiconductor memory element according to claim 1 ,
wherein said ferroelectric is a bismuth layered perovskite type ferroelectric substance.

4. The semiconductor memory element according to claim 1 ,
wherein said partition wall comprises a lamination of two or more materials having different etching rates to the wet etching or ion-reactive-plasma dry etching a protruding structure.

5. The semiconductor memory element according to claim 1 ,
wherein said memory substance further comprises a buffer insulator having a higher dielectric constant than a dielectric constant of said partition wall between said semiconductor substrate and said ferroelectric.

6. The semiconductor memory element according to claim 1 ,
said source region, said drain region, and a channel region are portions of said semiconductor not overlapping each other,
the channel region is sandwiched between said source region and said drain region,
said channel region is in contact with the bottom surface of said memory substance, and
the area of said bottom surface shares boundaries with said source region and with said drain region individually.

7. A memory cell array, comprising:
a plurality of memory cells, each memory cell being the semiconductor memory element according to claim 6 , the memory cells being arranged at regular intervals in rows and columns in a plane parallel to said semiconductor substrate, the number of the rows and columns being two or more;
a plurality of gate lines lying along the rows, each gate line being assigned to a separate row of memory cells, the gate line being connected with said conductors of the memory cells belonging to the row; and
pairs of drain lines and source lines lying along the columns and across the rows, each drain line being assigned to a separate column of memory cells, said drain regions of the memory cells belonging to a column are extended and merged with the corresponding drain line, an active region is used for electric transmission between the drain regions and the drain lines without via contacts, each source line being assigned to a separate column of memory cells, said source regions of the memory cells belonging to a column are extended and merged with the corresponding source line, the active region being used for electric transmission between the source regions and the source lines without via contacts, the active region being defined as an electric-conductive region in a semiconductor excluding element isolation region.

8. The memory cell array according to claim 7 , wherein two adjacent columns of memory cells share a source line.

9. A memory cell array comprising:
two or more stacked layer units, each layer unit comprising said memory cell array according to claim 8 ,
wherein the two layers vertically adjacent in the normal direction of the substrate plane are paired with each other in the top-to-down inverted mirror image, and
upper and lower memory cells are located in plane symmetry with one of the gate lines interposed therebetween, sharing the gate line.

10. A memory cell array comprising:
two or more stacked layer units, each layer unit comprising said memory cell array according to claim 7 ,
wherein two layers of the layer units vertically adjacent in the normal direction of the substrate plane are paired with each other in the top-to-down inverted mirror image, and
upper and lower memory cells are located in plane symmetry with one of the gate lines interposed therebetween, sharing the gate line.

11. A production method of the semiconductor memory element of claim 1 , the production method comprising:
forming the buffer insulator on the semiconductor substrate;
forming a protruding structure erected on the buffer insulator which is formed on the semiconductor substrate, a projection area of said protruding structure on said semiconductor substrate covering a channel region,
said channel region being sandwiched with a source and a drain region,
said channel region, said source region, and said drain region being portions of said semiconductor not overlapping each other,
said protruding structure having a length (L) that is equal to or smaller than 100 nm,
said protruding structure having a height that is equal to or larger than double the length (L);

covering said protruding structure with the partition wall;
shaving said protruding structure covered with said partition wall in a direction from a top of said protruding structure to said semiconductor substrate;
selectively removing said protruding structure to form the groove having a width that is equal to or smaller than 100 nm in said partition wall;
forming the stacked ferroelectric in the groove, the stacked ferroelectric being taller than 2L in height (H); and
forming the stacked conductor on said stacked ferroelectric,
wherein H is the minimum distance between said stacked conductor and said buffer insulator, and
the semiconductor memory element has an intensity of the memory function which becomes stronger as d increases in the range of d≥L/(2k) and disappears when d<L/(2k),
where d: a controlled film thickness of the ferroelectric which is measured on a flat surface,
k: k=Vb/Va,
Va(nm/sec): a film forming speed on a horizontal plane, and
Vb(nm/sec): a film forming speed on an inner wall of the groove.

12. The production method according to claim 11 , wherein said ferroelectric is a bismuth layered perovskite type ferroelectric.

13. The production method according to claim 11 , wherein said protruding structure consists of organic substances, said partition wall consists of inorganic substances, and said protruding structure is selectively removed by an oxygen plasma etching.

14. The production method according to claim 11 , wherein the protruding structure consists of a lamination of two or more layers,
the method further comprising:
selectively removing said protruding structure comprises selectively removing the two or more layers except for the bottom layer.

15. The production method according to claim 11 , wherein said semiconductor substrate consists of a lamination of two

Assignees

• Aist
• Wacom R&D Corp
• Wacom

Inventors

• Takahashi Mitsue
• Sakai Shigeki
• Kusuhara Masaki
• Toda Masayuki
• Umeda Masaru
• Sasaki Yoshikazu

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/671

  the conductor having lateral variation in doping or structure · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title