Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11069702-B2
Application number	US-201816116814-A
Country	US
Kind code	B2
Filing date	Aug 29, 2018
Priority date	Mar 14, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a stack comprising a plurality of conductive layers stacked and separated from each other in a first direction;
an insulating layer provided above the stack;
a columnar portion extending through the plurality of conductive layers and the insulating layer in the first direction;
wherein the columnar portion includes a core layer extending through at least one of the conductive layers in the first direction, a first semiconductor layer located between the core layer and the plurality of conductive layers, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer that is located above the core layer and contacts the first semiconductor layer, and
wherein the second semiconductor layer includes a first region containing phosphorous, and a second region that contains carbon and phosphorous, and
the second region includes a first sub-region provided between the core layer and the first region of the second semiconductor layer in the first direction and a second sub-region provided between the insulating layer and the first region of the second semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first semiconductor layer contains carbon, and a carbon concentration in the first semiconductor layer is lower than a carbon concentration in the second region of the second semiconductor layer.

3. The semiconductor device according to claim 2 , wherein the carbon concentration in the first semiconductor layer decreases along the first direction as being distant away from the first sub-region of the second semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first region of the second semiconductor layer contains carbon, and a carbon concentration in the first region of the second semiconductor layer is lower than a carbon concentration in the second region of the second semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the carbon concentration in the first region of the second semiconductor layer decreases in the first direction as being distant away from the first sub-region of the second semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising a contact contacting the second semiconductor layer.

7. The semiconductor device according to claim 1 , wherein
the stack is provided on a substrate, and
a lowermost surface of the second semiconductor layer is farther from the substrate in the first direction than is an upper surface of the uppermost one of the conductive layers in the stack from the substrate in the first direction.

8. The semiconductor device according to claim 1 , wherein the carbon concentration in the first region of the second semiconductor layer decreases along a second direction that is perpendicular to the first direction as being distant away from the second sub-region of the second semiconductor layer.

9. The semiconductor device according to claim 1 , wherein a side surface of the second sub-region of the second semiconductor layer is in contact with the first semiconductor layer.

10. The semiconductor device according to claim 1 , wherein a side surface of the second sub-region of the second semiconductor layer is in contact with the memory layer.

11. The semiconductor device according to claim 1 , wherein a bottom surface of the second sub-region of the second semiconductor layer is in contact with the first semiconductor layer.

Assignees

• Toshiba Memory Corp

Inventors

• Sato Hiroyasu

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title