Molding compound and semiconductor package with a molding compound

Patent metadata

Field	Value
Publication number	US-11069626-B2
Application number	US-201916385337-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Apr 17, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.

First claim

What is claimed is:

1. A molding compound, comprising:
a matrix; and
a filler comprising filler particles,
wherein the filler particles each comprise a core comprising a semiconducting material and an electrically insulating cover,
wherein the core comprises one of: a doped monocrystalline silicon particle, and a silicon carbide particle.

2. The molding compound of claim 1 , wherein a doping concentration of the doped semiconducting material is greater than 1E18 cm −3 .

3. The molding compound of claim 1 , wherein the molding compound comprises at least 10 wt. % of the filler.

4. The molding compound of claim 3 , wherein the molding compound comprises between 60 wt. % and 90 wt. % of the filler.

5. The molding compound of claim 3 , wherein a thickness of the cover is between 2 nanometers and 400 nanometers.

6. The molding compound of claim 1 , wherein a particle size of the filling particles is between 10 micrometers and 100 micrometers.

7. The molding compound of claim 1 , wherein the matrix comprises one of an epoxy and silicone.

8. The molding compound of claim 1 , further comprising at least one of a catalyst, a mold release material, and a colorant.

9. A semiconductor arrangement comprising:
at least one semiconductor die comprising a semiconductor material; and
a molding compound according to claim 1 .

10. The semiconductor arrangement of claim 9 , wherein the filler particles comprise the same type of semiconductor material as the semiconductor die.

11. The semiconductor arrangement of claim 10 , wherein the at least one semiconductor die comprises at least one of monocrystalline silicon (Si) and monocrystalline silicon carbide (SiC).

12. The semiconductor arrangement of claim 9 , further comprising:
a carrier,
wherein the at least one semiconductor die is mounted to the carrier.

13. The semiconductor arrangement of claim 12 , wherein the semiconductor arrangement comprises a plurality of semiconductor dies mounted to the carrier.

14. The semiconductor arrangement of claim 9 , wherein the molding compound forms a package of the semiconductor arrangement.

15. The semiconductor arrangement of claim 9 , further comprising:
a housing,
wherein the molding compound at least partially fills the housing.

16. The molding compound of claim 1 , wherein the core comprises the doped monocrystalline silicon particle.

17. The molding compound of claim 1 , wherein the core comprises the silicon carbide particle, and wherein the silicon carbide particle has a doping concentration of higher than 1E18 cm −3 .

18. The molding compound of claim 1 , wherein the core comprises the silicon carbide particle, and wherein the silicon carbide particle has a doping concentration of lower than 1E14 cm −3 .

19. A molding compound, comprising:
a matrix; and
a filler comprising filler particles,
wherein the filler particles each comprise a core comprising a semiconducting material and an electrically insulating cover,
wherein the cover has a rough surface.

20. A molding compound, comprising:
a matrix; and
a filler comprising filler particles,
wherein the filler particles each comprise a metal core and an electrically insulating cover,
wherein the metal core is a particle of one of the following: aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), or titanium (Ti), and
wherein the electrically insulating cover comprises a metal oxide of the metal from the metal core.

Assignees

• Infineon Technologies Ag

Inventors

• Mauder Anton
• Hellmund Oliver
• Irsigler Peter
• Melzner Hanno
• Miethaner Stefan
• Schmidt Sebastian
• Schulze Hans-Joachim

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/473 Primary

  containing a filler · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title