Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate

Patent metadata

Field	Value
Publication number	US-11069620-B2
Application number	US-201716474585-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Mar 31, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

First claim

What is claimed is:

1. A die interconnect substrate, comprising:
a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die; and
a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure, and wherein the substrate interconnect extends from a level above the bridge die to a level below the bridge die,
wherein the multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material; and
wherein the multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

2. The die interconnect substrate according to claim 1 , wherein an average lateral dimension of the electrically insulating filler structure is larger than 5 μm.

3. The die interconnect substrate according to claim 1 , wherein an average lateral dimension of the electrically insulating filler structure is smaller than 15 μm.

4. The die interconnect substrate according to claim 1 , wherein the electrically insulating filler structure extends from a level of the front surface of the bridge die towards a level of the back surface of the bridge die.

5. The die interconnect substrate according to claim 1 , wherein at least part of the electrically insulating layer is located between a level of the front surface of the bridge die and a level of the back surface of the bridge die.

6. The die interconnect substrate according to claim 1 , wherein the electrically insulating filler structure is a polyimide-based or epoxy-based filler structure.

7. The die interconnect substrate according to claim 1 , wherein the electrically insulating layer is a build-up film layer.

8. The die interconnect substrate according to claim 1 , further comprising a via portion formed on the first bridge die pad, wherein a maximal lateral dimension of the via portion is less than 10 μm.

9. The die interconnect substrate according to claim 1 , wherein the electrically insulating filler structure comprises filler particles.

10. The die interconnect substrate according to claim 9 , wherein a concentration of the filler particles in the electrically insulating filler structure lies between 10% and 50% of the weight of the electrically insulating filler structure.

11. The die interconnect substrate according to claim 1 , wherein the multilayer substrate structure comprises filler particles.

12. The die interconnect substrate according to claim 11 , wherein a concentration of the filler particles in the multilayer substrate structure lies between 50% and 80% of the weight of the multilayer substrate structure.

13. An electrical device, comprising
a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die;
a first semiconductor device connected to the first bridge die pad; and
a second semiconductor device connected to the second bridge die pad,
wherein the die interconnect substrate further comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure, and wherein the substrate interconnect extends from a level above the bridge die to a level below the bridge die,
wherein the multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material, and
wherein the multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

14. The electrical device according to claim 13 , wherein the die interconnect substrate, the first semiconductor device and the second semiconductor device are arranged in a common package.

15. A method for forming a die interconnect substrate, the method comprising:
placing a bridge die in a cavity of a multilayer substrate structure, wherein the bridge die comprises at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die,
wherein the multilayer substrate structure comprises an electrically insulating layer forming a lateral surface of the multilayer substrate structure next to the cavity, wherein the electrically insulating layer comprises a first electrically insulating material, and
wherein the multilayer substrate structure further comprises a substrate interconnect, wherein a portion of the substrate interconnect is located at a level below the bridge die; and
forming an electrically insulating filler structure filling a gap located laterally between the bridge die and the multilayer substrate structure, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

16. The method according to claim 15 , wherein forming the electrically insulating filler structure comprises forming an electrically insulating filler layer at the lateral surface of the multilayer substrate structure, and removing at least part of the electrically insulating filler layer until the electrically insulating layer and the bridge die are exposed.

17. The method according to claim 16 , wherein removing at least part of the electrically insulating filler layer comprises etching the electrically insulating filler layer, wherein an etch rate of the electrically insulating filler layer is at least 100 times an etch rate of the electrically insulating layer.

18. The method according to claim 16 , wherein forming the electrically insulating filler layer comprises placing an electrically insulating laminate layer on the lateral surface of the multilayer structure and applying pressure to the electrically insulating laminate layer so that a portion of the electrically insulating laminate layer is pressed into the gap.

19. The method according to claim 15 , wherein the electrically insulating filler structure is a polyimide-based or epoxy-based filler structure.

20. The method according to claim 15 , wherein the electrically insulating layer is a build-up film layer.

21. The method according to claim 15 , further comprising forming a first via portion on the first bridge die pad and a second via portion on the second bridge die pad after forming the electrically insulating filler structure,
wherein each via portion is part of a bridge contact structure to be formed on a bridge die pad of the bridge die.

22. The method according to claim 21 , wherein forming the first via portion and the second via portion comprises:
forming a mask layer on the bridge die and removing portions of the mask layer to form openings exposing at least part of the first bridge die pad and at least part of the second bridge die pad by a lithographic process; and
forming electrically conductive material in the openings of the mask layer to form the firs

Assignees

• Intel Corp

Inventors

• May Robert Alan
• Darmawikarta Kristof
• Boyapati Sri Ranga Sai Sai

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title