Logic circuitry for a replicable print cartridge

US11068434B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11068434-B2
Application numberUS-202016781052-A
CountryUS
Kind codeB2
Filing dateFeb 4, 2020
Priority dateDec 3, 2018
Publication dateJul 20, 2021
Grant dateJul 20, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.

First claim

Opening claim text (preview).

The invention claimed is: 1. A logic circuitry package for association with a replaceable print cartridge, the logic circuitry package comprising: a timer; a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer; and logic circuitry to, in response to a first command encoding a time period, sent to a communication address of the logic circuitry package via the serial data bus interface by the printer: initiate a low voltage on the data contact; wait for a duration based on the time period, the timer to track the duration independent of a clock signal at the clock contact from the serial data bus; and after the duration, cause the data contact to assume a second voltage different than the low voltage. 2. The logic circuitry package according to claim 1 , wherein the logic circuitry is to remove the low voltage on the data contact after an end of the time period. 3. The logic circuitry package according to claim 1 , wherein the second voltage is a high voltage. 4. The logic circuitry package according to claim 1 , wherein the second voltage is a default voltage. 5. The logic circuitry package according to claim 1 , wherein the logic circuitry is to output an acknowledge message in response to the first command before initiating the low voltage on the data contact. 6. The logic circuitry package according to claim 1 , wherein the logic circuitry is to initiate the low voltage on the data contact at the beginning of the time period. 7. The logic circuitry package according to claim 1 , further including memory, the logic circuitry to write data from the serial data bus interface to the memory in response to a second command. 8. The logic circuitry package according to claim 1 , further including memory, the logic circuitry to read data from the memory and to transmit a data signal corresponding to the data via the serial data bus interface in response to a read request. 9. The logic circuitry package according to claim 1 , wherein the serial data bus interface is an I2C data bus interface. 10. The logic circuitry package according to claim 9 , wherein the logic circuitry is to: communicate via more than one I2C address over the I2C bus interface, receive a second command associated with temporarily using a different, secondary I2C address, the second command to identify a second time period, monitor the second time period using the timer, without reference to the clock signal over the clock contact, and respond to a third command directed to the secondary I2C address during the second time period. 11. A replaceable print cartridge comprising the logic circuitry package according to claim 1 . 12. A replaceable print cartridge couplable to a print apparatus, the replaceable print cartridge comprising: a reservoir to contain a print material; a timer; a serial data bus interface including a data contact and a clock contact, the serial bus interface couplable to a serial data bus of the print apparatus; and logic circuitry to respond to a first command to determine a location of the replaceable print cartridge coupled to the print apparatus, the first command specifying a time period, and the logic circuitry to: initiate a low voltage on the data contact; monitor a timer and wait for a time period tracked by the timer to expire, the time period tracked without reference to a clock signal at the clock contact from the serial data bus; maintain the low voltage on the data contact for a duration based on the time period; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. 13. The replaceable print cartridge according to claim 12 , wherein the logic circuitry is to remove the low voltage on the data contact after the end of the time period. 14. The replaceable print cartridge according to claim 12 , wherein the second voltage is a high voltage. 15. The replaceable print cartridge according to claim 12 , wherein the second voltage is a default voltage. 16. The replaceable print cartridge according to claim 12 , wherein the logic circuitry is to output an acknowledge message in response to the first command before initiating the low voltage on the data contact. 17. The replaceable print cartridge according to claim 12 , wherein the first command specifies a duration of the time period and the logic circuitry is to initiate the low voltage on the data contact at the beginning of the time period. 18. The replaceable print cartridge according to claim 12 , further including memory, the logic circuitry to write data from the serial data bus interface to the memory in response to a second command. 19. The replaceable print cartridge according to claim 12 , further including memory, the logic circuitry to read data from the memory and to transmit a data signal corresponding to the data via the serial data bus interface in response to a read request. 20. The replaceable print cartridge according to claim 12 , wherein the serial data bus interface is an I2C data bus interface. 21. The replaceable print cartridge according to claim 20 , wherein the logic circuitry is to: communicate via more than one I2C address over the I2C bus interface, receive a second command associated with temporarily using a different, secondary I2C address, the second command to identify a second time period, use the timer to monitor the second time period using the timer, without reference to the clock signal over the clock contact, and respond to a third command directed to the secondary I2C address during the second time period.

Assignees

Inventors

Classifications

  • Electronically readable memory · CPC title

  • Outer structure · CPC title

  • Details of contacts on the cartridge, e.g. protection of contacts · CPC title

  • using universal interface adapter · CPC title

  • details of transmission · CPC title

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What does patent US11068434B2 cover?
Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in respons…
Who is the assignee on this patent?
Hewlett Packard Development Co, Hewlett Packard Development Lp
What technology area does this patent fall under?
Primary CPC classification B41J2/17553. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jul 20 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).