Slave device bit sequence zero driver

Patent metadata

Field	Value
Publication number	US-9454504-B2
Application number	US-201414332323-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Sep 30, 2010
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A slave device to be connected to a master device by a data line comprises circuitry that, in response to receiving a command from the master device, drives a bit sequence comprising at least one zero.

First claim

What is claimed is:

1. An apparatus comprising:
a slave device to be connected to a master device by an I2C protocol multi-drop serial bus having a data line, wherein the slave device comprises an ink cartridge, the slave device comprising:
a non-volatile memory enabled ink cartridge associated with a printing system;
a memory location comprising circuitry to:
upon receiving a data byte at a scratch address within the memory location, send an acknowledge pulse over a data line;
in response to receiving and recognizing an address sequence as part of a transmitted bit sequence, send an analogue acknowledge pulse over the data line;
in response to receiving an address byte from the master device, send another an acknowledge pulse over the data line; and
transmit the data byte stored at the scratch address by driving the data line.

2. The apparatus of claim 1 , wherein the data byte comprises all data zeros.

3. The apparatus of claim 1 , wherein the data byte stored at the scratch address contains at least one data zero.

4. The apparatus of claim 1 , wherein the data zero transmitted by the circuitry has a voltage outside of a data transfer voltage range.

5. The apparatus of claim 4 , wherein the data zero has a voltage above 0 V and below 1 V.

6. The apparatus of claim 1 , wherein the circuitry is to, in response to receiving and not recognizing the address sequence as part of the transmitted bit sequence, ignore subsequent transmissions until after the next STOP signal is received from the master device.

7. The apparatus of claim 1 , wherein the circuitry is to not generate an acknowledge pulse after transmitting the data byte stored at the scratch address.

8. The apparatus of claim 1 , wherein the slave device has four connectors, comprising power, ground, data and clock.

9. A print cartridge comprising:
a supply of ink;
circuitry to communicate across a shared serial bus and
(a) store, in a memory, a bit sequence received from the master device and devoid of an assigned meaning based upon a pattern of the bit sequence, the bit sequence comprising at least one data zero;
(b) transmit an acknowledgment pulse to the master device; and
(c) in response to receiving a command from the master device along a serial bus and following the transmission of the acknowledgment pulse, drive signals representing the bit sequence to the master device, wherein the at least one data zero of the bit sequence corresponds to a time during which the master device measures a specific voltage level of the signals and assigns one of multiple values to the signals based upon the voltage level of the signals corresponding in time to the at least one data zero.

10. The print cartridge of claim 9 , wherein the bit sequence comprises all data zeros.

11. The apparatus of claim 9 , wherein the circuitry communicates according to an I2C protocol.

12. The apparatus of claim 9 , further comprising (a) storing, with the print cartridge, the bit sequence received from the master device, (b) the transmission of the acknowledgment pulse to the master device and (c) the driving of the signals representing the bit sequence to the master device are consecutive.

13. The apparatus of claim 9 , wherein the circuitry is to transmit the bit sequence represented by the signals to the master device without associating any meaning to the bit sequence.

14. A method for detecting a physical location of the slave device over and I2C protocol multi-drop serial bus, the slave device including a nonvolatile memory enabled ink cartridge having a memory location, the method comprising:
sending an acknowledge pulse over a data line after receiving a data byte at a scratch address within the memory location,
sending an acknowledge pulse over the data line in response to receiving and recognizing an address sequence as part of a transmitted bit sequence,
sending another an acknowledge pulse over the data line in response to receiving an address byte from the master device, and
transmitting the byte stored at the scratch address by driving the data line.

15. The method of claim 14 , wherein the byte stored at the scratch address comprises all zeros.

16. The method of claim 14 , wherein the data byte stored at the scratch address contains at least one data zero.

Assignees

• Hewlett Packard Development Co Lp

Inventors

• Evans Duane Martin

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title