Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Patent metadata

Field	Value
Publication number	US-11068339-B2
Application number	US-201916417555-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	Jul 2, 2016
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A processor comprising:
a decode unit to decode a read from memory instruction, the read from memory instruction to indicate a source memory operand and a destination storage location; and
an execution unit coupled with the decode unit, the execution unit, in response to the decode of the read from memory instruction, to:
read data from the source memory operand;
store an indication of defective data in an architecturally visible storage location, when the data is defective, wherein the architecturally visible storage location is one selected from a group consisting of a general-purpose register and at least one condition code bit; and
complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective.

2. The processor of claim 1 , wherein the execution unit, in response to the decode of the read from memory instruction, is to read the data from a block storage memory location, which is to be in a physical memory address space that is addressable by the read from memory instruction, and wherein the processor comprises a general-purpose central processing unit (CPU).

3. The processor of claim 1 , wherein the decode unit is to decode a second read from memory instruction, which is to have a same opcode as the read from memory instruction, and which is to indicate a second source memory operand and a second destination storage location, and wherein the execution unit, in response to the decode of the second read from memory instruction, is to:
read second data from the second source memory operand;
store the second data to the second destination storage location, when the second data is not defective; and
store an indication that the second data is not defective in an architecturally visible storage location, when the second data is not defective.

4. The processor of claim 1 , wherein the execution unit, in response to the decode of the read from memory instruction, before the indication of the defective data is stored, is to determine whether the data that is defective was read from a block storage memory location.

5. The processor of claim 4 , wherein the execution unit, in response to the decode of the read from memory instruction, is to determine to store the indication of the defective data, when the data is defective, and when the data that is defective was read from the block storage memory location.

6. The processor of claim 5 , wherein the decode unit is to decode a second read from memory instruction, which is to have a same opcode as the read from memory instruction, and which is to indicate a second source memory operand, and wherein the execution unit, in response to the decode of the second read from memory instruction, is to:
read second data from the second source memory operand;
determine that the second data was not read from a block storage memory location, when the second data is defective; and
cause an exceptional condition before completing execution of the second read from memory instruction.

7. The processor of claim 6 , wherein the execution unit, in response to the decode of the second read from memory instruction, is to cause the exceptional condition, which is to be a machine check exception.

8. The processor of claim 1 , further comprising logic to detect that the data is defective based on at least one of a data parity error and an error correction code (ECC) error.

9. The processor of claim 1 , wherein the decode unit is also to decode a second read from memory instruction, which is to have been included in an instruction set prior to the read from memory instruction, and wherein the processor, in response to the decode of the second read from memory instruction, is to cause an exceptional condition, when data that is defective is read.

10. The processor of claim 1 , wherein the decode unit is to decode the read from memory instruction that is to indicate the general-purpose register as the architecturally visible storage location.

11. The processor of claim 1 , wherein the decode unit is to decode the read from memory instruction that is to indicate the least one condition code bit as the architecturally visible storage location.

12. The processor of claim 1 , wherein the decode unit is to decode the read from memory instruction that is to indicate the destination storage location that is to be a destination memory operand, and wherein the read from memory instruction is to indicate a second architecturally visible storage location that is to store an amount of data that is to be stored from the source memory operand to the destination memory operand.

13. The processor of claim 12 , wherein the execution unit, in response to the decode of the read from memory instruction, is to store an updated amount of data in the second architecturally visible storage location, the updated amount of data to indicate how much of the amount of data has been stored to the destination storage location when the data that is defective was read.

14. A method performed by a processor comprising:
receiving a read from memory instruction, the read from memory instruction indicating a source memory operand and a destination storage location;
performing the read from memory instruction, including:
reading data from the source memory operand;
storing an indication of defective data in an architecturally visible storage location, when the data is defective, wherein the architecturally visible storage location is a general-purpose register, at least one condition code bit, or a combination thereof; and
completing execution of the read from memory instruction without causing an exceptional condition, when the data is defective.

15. The method of claim 14 , further comprising:
receiving a second read from memory instruction having a same opcode as the read from memory instruction, and indicating a second source memory operand and a second destination storage location;
performing the second read from memory instruction, including:
reading second data from the second source memory operand;
storing the second data to the second destination storage location, when the second data is not defective; and
storing an indication that the second data is not defective in an architecturally visible storage location, when the second data is not defective.

16. The method of claim 14 , further comprising, before storing the indication of the defective data, determining whether the data that is defective was read from a block storage memory location.

17. The method of claim 16 , further comprising determining to store the indication of the defective data, when the data is defective, and when the data that is defective was read from the block storage memory location, wherein a determination would be made to cause an exceptional condition if the defective data was instead not read from the block storage memory location.

18. The method of claim 14 , wherein said receiving comprises receiving the read from memory instruction indicating the destination storage location which is a destination memory operand, and indicating a second architecturally visible storage location storing an indication of an amount of data to be stored from the source memory operand to the destination memory operand.

19. A processor comprising:
decode circuitry to decode a read from memory instruction, the read from memory instruction to indicate a source memory operand and a destination storage location; and
execution circuitry coupled with the decode circuitry, the execution circuitry

Assignees

• Intel Corp

Inventors

• Raj Ashok
• Gabor Ron
• Shafi Hisham
• Ghetie Sergiu
• Kumar Mohan J
• Yigzaw Theodros
• Jayakumar Sarathy
• Upasani Neeraj S

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title