Multiplier circuit

Patent metadata

Field	Value
Publication number	US-11068238-B2
Application number	US-201916417866-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	May 21, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

First claim

The invention claimed is:

1. A multiplier circuit comprising:
a carry-save adder (CSA) network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value represented using a carry-save representation, the CSA network comprising:
a first stage of carry-save adders to perform a first subset of the partial product additions using selected portions of the partial products to generate a plurality of sub-products; and
at least one further stage of carry-save adders to perform a further subset of the partial product additions using the plurality of sub-products generated by the first stage and remaining portions of the partial products, to generate the redundant result value;

sub-product processing circuitry to apply a processing function to the plurality of sub-products generated by the first stage of carry-save adders, to generate processed sub-products represented using the carry-save representation, said processing function comprising at least one operation other than addition; and
input control circuitry to inject the processed sub-products as inputs to a subset of carry-save adders of said at least one further stage, to provide a sum-of-processed-sub-products mode in which the redundant result value generated by said at least one further stage represents a sum of the processed sub-products generated by the sub-product processing circuitry.

2. The multiplier circuit according to claim 1 , in which the input control circuitry is configured to inject, as inputs to said subset of carry-save adders of said at least one further stage:
in said sum-of-processed-sub-products mode, the processed sub-products generated by the sub-product processing circuitry; and
in a multiplication mode, inputs depending on at least one of:
the sub-products generated by the first stage of carry-save adders;
results of earlier carry-save adders of said at least one further stage; and
said remaining portions of the partial products.

3. The multiplier circuit according to claim 2 , in which the multiplier circuit is configured to use the same hardware circuits of said subset of carry-save adders both for:
said further subset of the partial product additions for generating said redundant result value in the multiplication mode; and
addition of the processed sub-products in the sum-of-processed-sub-products mode.

4. The multiplier circuit according to claim 2 , in which in the multiplication mode, the redundant result value comprises one or more elements each representing a product of a respective pair of elements of a first operand and a second operand.

5. The multiplier circuit according to claim 4 , comprising SIMD control circuitry to control, based on a selected data element size of said one or more elements of the first operand and second operand, at least one of:
zeroing of portions of the partial products; and
propagation of carries between respective carry-save adders of the CSA network.

6. A data processing apparatus comprising:
the multiplier circuit according to claim 2 ; and
an instruction decoder to decode a program instruction to generate control signals to control the multiplier circuit; in which:
in response to a multiply instruction, the instruction decoder is configured to generate control signals to control the input control circuitry to operate in the multiplication mode; and
in response to a sum-of-processed-sub-products instruction, the instruction decoder is configured to generate control signals to control the input control circuitry to operate in the sum-of-processed-sub-products mode.

7. The multiplier circuit according to claim 1 , in which said at least one further stage of carry-save adders comprises second and third stages of carry-save adders to perform second and third subsets of the partial product additions, where in a multiplication mode the third stage is configured to perform the third subset of the partial product additions dependent on results of said second subset of partial product additions performed by the second stage; and
said subset of carry-save adders are in said third stage of carry-save adders.

8. The multiplier circuit according to claim 7 , in which the second stage of carry-save adders is configured to perform the second subset of the partial product additions in parallel with the sub-product processing circuitry applying said processing function to the plurality of sub-products.

9. The multiplier circuit according to claim 1 , in which the at least one further stage of carry-save adders comprises a plurality of lanes of carry-save adders, each lane of carry-save adders to generate bit values of a corresponding part of the redundant result value; and
said subset of carry-save adders are provided in a most significant subset of said plurality of lanes of carry-save adders, said most significant subset excluding at least one lane of carry-save adders for generating a least significant part of the redundant result value.

10. The multiplier circuit according to claim 1 , comprising a carry-propagate adder to add a sum term and a carry term of the redundant result value to generate a non-redundant result value represented in a non-redundant representation.

11. The multiplier circuit according to claim 1 , comprising partial product generating circuitry to generate the plurality of partial products based on a first operand and a second operand; in which
each of the plurality of sub-products corresponds to a product of a respective pair of selected portions of the first and second operands.

12. The multiplier circuit according to claim 1 , in which the processing function comprises an alignment shift to align the plurality of sub-products.

13. The multiplier circuit according to claim 12 , in which the sub-product processing circuitry comprises:
shift amount calculating circuitry to calculate a shift amount based on further portions of the first and second operands; and
shift circuitry to shift a given sub-product of the plurality of sub-products by a number of bit positions depending on the shift amount calculated by the shift amount calculating circuitry.

14. The multiplier circuit according to claim 13 , in which said partial product generating circuitry is configured to select:
as said selected portions, portions of the first and second operands representing fractions of a plurality of floating-point values represented in a floating-point representation; and
as said further portions, portions of the first and second operands representing exponents of said plurality of floating-point values.

15. The multiplier circuit according to claim 14 , in which said floating-point representation is a truncated-precision floating-point representation having the same number of exponent bits as a full-precision floating-point representation and a smaller number of fraction bits than the full-precision floating-point representation.

16. The multiplier circuit according to claim 13 , in which the shift circuitry comprises a plurality of shift stages including at least:
a first shift stage to perform a stage one shift operation on the given sub-product depending on a least significant portion of the shift amount calculated by the shift amount calculating circuitry; and
a second shift stage to perform a stage two shift operation on the given sub-product or a result of the first shift stage, depending on a more significant portion of the shift amount calculated by the shift amount calculating circuitry; and
the first shift stage is configured to perform the stage one shi

Assignees

• Advanced Risc Mach Ltd

Inventors

• Kennedy Michael Alexander
• Burgess Neil
• Xie Zichao
• PATHIRANE Chiloda Ashan Senarath

Classifications

• G06F7/509

  for multiple operands, e.g. digital integrators · CPC title

• G06F7/5277

  with column wise addition of partial products · CPC title

• G06F7/5312 Primary

  using carry save adders · CPC title

• G06F7/5272

  with row wise addition of partial products · CPC title