Adaptive integrated programmable device platform

Patent metadata

Field	Value
Publication number	US-11063594-B1
Application number	US-202016872009-A
Country	US
Kind code	B1
Filing date	May 11, 2020
Priority date	Mar 27, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface;
a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface;
a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface; and
wherein the first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.

2. The integrated circuit of claim 1 , wherein the first interface is configured to allocate a first physical function to each tenant of the plurality of tenants.

3. The integrated circuit of claim 1 , wherein the first interface includes a plurality of Peripheral Component Interconnect Express (PCIe) controllers, wherein each tenant of the plurality of tenants is allocated a PCIe controller of the plurality of PCIe controllers.

4. The integrated circuit of claim 1 , wherein the second interface is shared among the plurality of tenants while maintaining isolation among the plurality of tenants.

5. The integrated circuit of claim 1 , wherein the second interface includes a plurality of Ethernet interface controllers and a plurality of inputs/outputs, and wherein each tenant of the plurality of tenants has a dedicated Ethernet interface controller of the plurality of Ethernet interface controllers and dedicated inputs/outputs of the plurality of inputs/outputs.

6. The integrated circuit of claim 1 , wherein the programmable logic circuitry implements a plurality of hardware accelerated functions and at least one of the plurality of hardware accelerated functions corresponds to each tenant of the plurality of tenants.

7. The integrated circuit of claim 1 , wherein the one or more hardware accelerated functions include cryptography.

8. The integrated circuit of claim 1 , wherein the one or more hardware accelerated functions include machine learning.

9. The integrated circuit of claim 1 , wherein the one or more hardware accelerated functions include image processing.

10. The integrated circuit of claim 1 , further comprising:
a hardwired circuit block configured to implement a selected hardware accelerated function for a selected tenant of the plurality of tenants;
wherein the programmable logic circuitry implements a circuit block configured for use with the selected tenant; and
wherein the hardwired circuit block and the circuit block of the programmable logic circuitry use a common descriptor definition.

11. The integrated circuit of claim 10 , wherein the circuit block of the programmable logic circuitry implements the selected hardware accelerated function for the selected tenant.

12. The integrated circuit of claim 10 , further comprising:
a processor configured to execute program code, wherein the processor uses the common descriptor definition.

13. The integrated circuit of claim 10 , further comprising:
a data processing engine array including a plurality of data processing engines, wherein the plurality of data processing engines use the common descriptor definition.

14. The integrated circuit of claim 10 , wherein the hardwired circuit block is one of a plurality of hardwired circuit blocks each including a cryptography engine, wherein each cryptography engine uses the common descriptor definition.

15. The integrated circuit of claim 10 , wherein each of the hardwired circuit block and the circuit block of the programmable logic circuitry is configured to provide isolation from other ones of the plurality of tenants.

16. The integrated circuit of claim 1 , further comprising:
a hardwired circuit block configured to implement a selected hardware accelerated function for a selected tenant of the plurality of tenants;
wherein the programmable logic circuitry implements a circuit block configured to implement the selected hardware accelerated function for the selected tenant; and
wherein the selected hardware accelerated function is remapped from the hardwired circuit block to the circuit block in the programmable circuitry or from the circuit block in the programmable circuitry to the hardwired circuit block.

17. The integrated circuit of claim 16 , wherein the circuit block of the programmable circuitry and the hardwired circuit block have common interfaces.

18. The integrated circuit of claim 16 , wherein the hardwired circuit block and the circuit block of the programmable circuitry use a common descriptor definition.

19. The integrated circuit of claim 16 , wherein isolation is maintained among the plurality of tenants during the remapping.

20. The integrated circuit of claim 16 , wherein the selected hardware acceleration function is remapped without disrupting operation of the selected tenant.

Assignees

• Xilinx Inc

Inventors

• Ahmad Sagheer
• Dastidar Jaideep
• Gaide Brian C
• Noguera Serra Juan J
• Swarbrick Ian A

Classifications

• H03K19/1776

  for memories · CPC title

• H03K19/17756

  for partial configuration or partial reconfiguration · CPC title

• H03K19/17736 Primary

  Structural details of routing resources · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/17712

  one of the matrices at least being reprogrammable · CPC title