Semiconductor devices including a metal silicide layer and methods for manufacturing thereof

US11063014B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11063014-B2
Application numberUS-201916413195-A
CountryUS
Kind codeB2
Filing dateMay 15, 2019
Priority dateMay 16, 2018
Publication dateJul 13, 2021
Grant dateJul 13, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a silicon layer; a metal silicide layer disposed directly on the silicon layer; and a solder layer disposed directly on the metal silicide layer, the solder layer comprising a silicide-forming metal which corresponds to the metal of the metal silicide layer, wherein the solder layer comprises a tin-silver solder alloy. 2. The semiconductor device of claim 1 , wherein the metal silicide layer comprises at least one of titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten silicide, molybdenum silicide, zirconium silicide, and tantalum silicide. 3. The semiconductor device of claim 1 , wherein the metal silicide layer comprises Me x Si y , where x has a value of 1, 2 or 5 and where y has a value of 1, 2 or 3. 4. The semiconductor device of claim 1 , wherein the solder layer comprises a rare-earth metal. 5. The semiconductor device of claim 4 , wherein the rare-earth metal comprises at least one of cerium, scandium, lanthanum, praseodymium, promethium, neodymium, samarium, and europium. 6. The semiconductor device of claim 1 , wherein a thickness of the metal silicide layer is in a range from 100 nanometers to 1000 nanometers. 7. The semiconductor device of claim 1 , further comprising: an ohmic contact formed between the silicon layer and the metal silicide layer. 8. The semiconductor device of claim 1 , further comprising: a solder contact formed between the solder layer and a metal component, the metal component comprising at least one of a leadframe, a die pad, a connection lead, a clip, a metal foil. 9. The semiconductor device of claim 1 , wherein the silicon layer is part of a silicon transistor or a silicon diode.

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What does patent US11063014B2 cover?
A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10D64/62. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 13 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).