Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Patent metadata

Field	Value
Publication number	US-11062203-B2
Application number	US-201615394897-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.

First claim

What is claimed is:

1. A processor comprising:
a memory to store a plurality of synapse weights of a neural network, the memory comprising a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight;
at least one neuron core comprising logic associated with a plurality of neurons;
a synapse memory mapping engine to:
receive a selection of a neural network topology type;
identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
map the plurality of synapse weights to locations in the memory based on the identified synapse memory mapping scheme; and

when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.

2. The processor of claim 1 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.

3. The processor of claim 2 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.

4. The processor of claim 1 , wherein the processor is to access synapse weights connected to a neuron of the processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron.

5. The processor of claim 1 , wherein the identified synapse memory mapping scheme specifies a pseudorandom sparse connectivity scheme for a first group of rows of the memory.

6. The processor of claim 1 , wherein the identified synapse memory mapping scheme specifies a location for a synapse weight of the plurality of synapse weights based on an arithmetic operation including a position of the synapse weight within an ordered list of synapse weights and a position of a neuron connected to the synapse weight within an ordered list of neurons.

7. The processor of claim 1 , wherein the memory comprises a plurality of memory elements distributed among a plurality of synaptic cores of a network on chip.

8. A method comprising:
receiving a selection of a neural network topology type;
identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme;
wherein the memory comprises a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight; and
wherein, when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.

9. The method of claim 8 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.

10. The method of claim 9 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.

11. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
receive a selection of a neural network topology type;
identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
map a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme;
wherein the memory comprises a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight; and
wherein, when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.

12. The medium of claim 11 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.

13. The medium of claim 12 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.

14. The medium of claim 11 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron.

15. The medium of claim 11 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of

Assignees

• Intel Corp

Inventors

• Chen Gregory K
• Kumar Raghavan
• Sumbul Huseyin Ekin
• Knag Phil
• Krishnamurthy Ram K

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0475

  Generative networks · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title