Recovering from write cache failures in servers

Patent metadata

Field	Value
Publication number	US-11061818-B1
Application number	US-202016820295-A
Country	US
Kind code	B1
Filing date	Mar 16, 2020
Priority date	Mar 16, 2020
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A computer-implemented method, according to one embodiment, includes: in response to experiencing a power loss event, resupplying power to NVRAM which includes a write cache. In response to detecting that the NVRAM has experienced a failure event, the NVRAM is temporarily guarded from further use. Moreover, a portion of volatile memory is allocated to serve as a temporary write cache. The allocated portion of volatile memory is also cleared. A determination is made as to whether data is present in the write cache in the NVRAM, and in response to determining that data is present in the write cache, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM are marked as having experienced data loss. Furthermore, a warning is sent which indicates that data loss has been experienced by the one or more marked volumes in the memory.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
in response to experiencing a power loss event, resupplying power to non-volatile random access memory (NVRAM), wherein the NVRAM includes a write cache;
in response to detecting that the NVRAM has experienced a failure event, temporarily guarding the NVRAM from further use;
allocating a portion of volatile memory to serve as a temporary write cache;
indicating that the temporary write cache has been allocated from volatile memory;
clearing the allocated portion of volatile memory;
determining whether data is present in the write cache in the NVRAM;
in response to determining that data is present in the write cache in the NVRAM, marking one or more volumes in memory which correspond to the data present in the write cache in the NVRAM as having experienced data loss; and
sending a warning which indicates that data loss has been experienced by the one or more marked volumes in the memory.

2. The computer-implemented method of claim 1 , wherein determining whether data is present in the write cache in the NVRAM includes:
accessing metadata stored in the memory which indicates whether data was present in the write cache in the NVRAM when the power loss event was experienced.

3. The computer-implemented method of claim 1 , wherein the processes are performed by a first server, wherein the first server is electrically coupled to a second server.

4. The computer-implemented method of claim 3 , comprising:
determining whether the temporary write cache in the volatile memory should be maintained while the NVRAM remains guarded from further use; and
in response to determining that the temporary write cache in the volatile memory should be maintained while the NVRAM remains guarded from further use, maintaining operation of the first and second servers.

5. The computer-implemented method of claim 4 , comprising:
in response to determining that the temporary write cache in the volatile memory should not be maintained while the NVRAM remains guarded from further use, temporarily guarding the first server from further use; and
maintaining operation of the second server.

6. The computer-implemented method of claim 1 , wherein the NVRAM includes a non-volatile dual in-line memory module (NVDIMM).

7. The computer-implemented method of claim 6 , wherein the volatile memory includes a dual in-line memory module.

8. The computer-implemented method of claim 1 , wherein indicating that the temporary write cache has been allocated from volatile memory includes:
setting a microcode flag as a global code variable for an initial microcode load (IML) sequence.

9. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to:
in response to experiencing a power loss event, resupply, by the processor, power to non-volatile random access memory (NVRAM), wherein the NVRAM includes a write cache;
in response to detecting that the NVRAM has experienced a failure event, temporarily guard, by the processor, the NVRAM from further use;
allocate, by the processor, a portion of volatile memory to serve as a temporary write cache;
indicate, by the processor, that the temporary write cache has been allocated from volatile memory;
clear, by the processor, the allocated portion of volatile memory;
determine, by the processor, whether data is present in the write cache in the NVRAM;
in response to determining that data is present in the write cache in the NVRAM, mark, by the processor, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM as having experienced data loss; and
send, by the processor, a warning which indicates that data loss has been experienced by the one or more marked volumes in the memory.

10. The computer program product of claim 9 , wherein determining whether data is present in the write cache in the NVRAM includes:
accessing metadata stored in the memory which indicates whether data was present in the write cache in the NVRAM when the power loss event was experienced.

11. The computer program product of claim 9 , wherein the processor is included in a first server, wherein the first server is electrically coupled to a second server.

12. The computer program product of claim 11 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:
determine, by the processor, whether the temporary write cache in the volatile memory should be maintained while the NVRAM remains guarded from further use; and
in response to determining that the temporary write cache in the volatile memory should be maintained while the NVRAM remains guarded from further use, maintain, by the processor, operation of the first and second servers.

13. The computer program product of claim 12 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:
in response to determining that the temporary write cache in the volatile memory should not be maintained while the NVRAM remains guarded from further use, temporarily guard, by the processor, the first server from further use; and
maintain, by the processor, operation of the second server.

14. The computer program product of claim 9 , wherein the NVRAM includes a non-volatile dual in-line memory module (NVDIMM).

15. The computer program product of claim 14 , wherein the volatile memory includes a dual in-line memory module.

16. The computer program product of claim 9 , wherein indicating that the temporary write cache has been allocated from volatile memory includes:
setting a microcode flag as a global code variable for an initial microcode load (IML) sequence.

17. A system, comprising:
a plurality of non-volatile random access memory (NVRAM) blocks configured to store data;
a processor; and
logic integrated with and/or executable by the processor, the logic being configured to:
in response to experiencing a power loss event, resupply, by the processor, power to non-volatile random access memory (NVRAM), wherein the NVRAM includes a write cache;
in response to detecting that the NVRAM has experienced a failure event, temporarily guard, by the processor, the NVRAM from further use;
allocate, by the processor, a portion of volatile memory to serve as a temporary write cache;
indicate, by the processor, that the temporary write cache has been allocated from volatile memory;
clear, by the processor, the allocated portion of volatile memory;
determine, by the processor, whether data is present in the write cache in the NVRAM;
in response to determining that data is present in the write cache in the NVRAM, mark, by the processor, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM as having experienced data loss; and
send, by the processor, a warning which indicates that data loss has been experienced by the one or more marked volumes in the memory.

18. The system of claim 17 , wherein determining whether data is present in the write cache in the NVRAM includes:
accessing metadata stored in the memory which indicates whether data was present in the write cache in the NVRAM when the power loss event was experienced.

19. The system of claim 17 , wherein the processor is included in a first server, wherein the first server is electrically coupled to a second server, wherein the logic is co

Assignees

• IBM

Inventors

• Sorenson Todd C
• Nguyen Trung N
• Ash Kevin J
• Rasor Louis A

Classifications

• G06F9/5016

  the resource being the memory · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title