Display module having glass substrate on which side wirings are formed and manufacturing method of the same

US11056630B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11056630-B2
Application numberUS-202016786514-A
CountryUS
Kind codeB2
Filing dateFeb 10, 2020
Priority dateFeb 13, 2019
Publication dateJul 6, 2021
Grant dateJul 6, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display module includes a glass substrate having a front surface and a back surface opposite to the front surface; a TFT layer; LEDs mounted on the TFT layer; and a plurality of side wirings formed at intervals in an edge area of the glass substrate, and the edge area includes a first area corresponding to a side surface of the glass substrate, a second area adjacent to the side surface, and a third area adjacent to the side surface, and a first chamfered surface formed by chamfering a corner at which the first area and the second area meet, and a second chamfered surface formed by chamfering a corner at which the first area and the third area meet, and each of the plurality of side wirings is disposed along the second area, the first chamfered surface, the first area, the second chamfered surface, and the third area.

First claim

Opening claim text (preview).

What is claimed is: 1. A display module comprising: a glass substrate of a quadrangle type having a front surface and a back surface opposite to the front surface; a thin film transistor (TFT) layer formed on the front surface of the glass substrate; a plurality of light emitting diodes (LEDs) mounted on the TFT layer; and a plurality of side wirings formed at intervals in an edge area of the glass substrate, wherein the edge area comprises: a first area corresponding to a side surface of the glass substrate; a second area adjacent to the side surface of the glass substrate in the front surface of the glass substrate; a third area adjacent to the side surface of the glass substrate in the back surface of the glass substrate; a first chamfered surface formed at a corner at which the first area and the second area meet; and a second chamfered surface formed at a corner at which the first area and the third area meet, and wherein each of the plurality of side wirings is disposed along the second area, the first chamfered surface, the first area, the second chamfered surface, and the third area. 2. The display module as claimed in claim 1 , wherein a height of the first chamfered surface is less than 10% of a thickness of the glass substrate. 3. The display module as claimed in claim 1 , wherein a height of the second chamfered surface is less than 10% of a thickness of the glass substrate. 4. The display module as claimed in claim 1 , wherein the plurality of side wirings are formed by screen printing with conductive ink. 5. The display module as claimed in claim 1 , wherein one end portion of each of the plurality of side wirings is electrically connected to a first connection pad disposed in the second area, and wherein another end portion of each of the plurality of side wirings is electrically connected to a second connection pad disposed in the third area, and wherein the first connection pad is connected to a pixel driving circuit of the TFT layer, and the first connection pad is connected to a driver Integrated Circuit disposed in a rear surface of a glass substrate. 6. The display module as claimed in claim 1 , further comprising a plurality of connection pads formed in the edge area and electrically connected to the plurality of side wirings, and an insulating layer having grooves and disposed on the plurality of connection pads, the plurality of connection pads formed in the edge area being partially exposed by the grooves of the insulating layer. 7. A display module comprising: a glass substrate of a quadrangle type having a front surface and a back surface opposite to the front surface; a thin film transistor (TFT) layer formed on the front surface of the glass substrate; a plurality of light emitting diodes (LEDs) mounted on the TFT layer; and a plurality of side wirings disposed along edge areas of at least two sides of the glass substrate, the plurality of side wirings being disposed at substantially equal intervals, wherein the glass substrate includes a chamfered surface through which the plurality of side wirings pass and the chamfered surface is formed at a corner of each of the edge areas of the at least two sides. 8. The display module as claimed in claim 7 , wherein the edge areas of the at least two sides correspond to a pair of opposing sides in the glass substrate, respectively. 9. The display module as claimed in claim 7 , wherein the edge areas of the at least two sides correspond to a pair of adjacent sides in the glass substrate, respectively. 10. The display module as claimed in claim 7 , wherein the number of the plurality of side wirings is equal to or less than the number of LEDs mounted on the TFT layer. 11. A manufacturing method of a display module, the manufacturing method comprising: forming a thin film transistor (TFT) layer on a glass substrate; forming a chamfered surface at a corner of at least one edge area of edge areas of the glass substrate; forming a plurality of side wirings electrically connected to a plurality of connection pads disposed in an edge of the TFT layer in the at least one edge area of the glass substrate in which the chamfered surface is formed; and transferring a plurality of light emitting diodes (LEDs) onto the TFT layer. 12. The manufacturing method as claimed in claim 11 , wherein the chamfered surface is formed to have a height less than 10% of a thickness of the glass substrate. 13. The manufacturing method as claimed in claim 11 , wherein an inclination angle of the chamfered surface is less than 45 degrees with respect to an imaginary plane extending from a side surface of the glass substrate. 14. The manufacturing method as claimed in claim 11 , wherein the plurality of side wirings are formed by one of a laser patterning process, a pad printing process, an ink screening process, and a sputtering process. 15. The manufacturing method as claimed in claim 11 , wherein in the forming of the plurality of side wirings, the plurality of side wirings are formed at positions corresponding to a pair of opposing sides in the glass substrate, respectively. 16. The manufacturing method as claimed in claim 11 , wherein in the forming of the plurality of side wirings, the number of the plurality of side wirings is formed to be equal to or less than the number of LEDs mounted on the TFT layer. 17. The manufacturing method as claimed in claim 11 , wherein the forming the plurality of side wirings comprises: forming a metal film on the edge area and a side surface of the glass substrate; irradiating, by a laser beam irradiator, a laser beam on the metal film from an end of the metal film to a middle portion of the chamfered surface; rotating the glass substrate relative to the laser beam irradiator; and irradiating, by the laser beam irradiator, the laser beam on the metal film from the middle portion of the chamfered surface to the side surface. 18. The manufacturing method as claimed in claim 11 , wherein the forming the plurality of side wirings comprises: preparing a carrier film having a plurality of conductive ribbons; disposing the carrier film on the edge area; performing a thermal compressing on the edge area; and removing the carrier film with the plurality of conductive ribbons remaining in the edge area. 19. The manufacturing method as claimed in claim 11 , wherein the forming the plurality of side wirings comprises: preparing a three-dimensional pad having a plurality of conductive ribbons; disposing the three-dimensional pad on the edge area; pressing the three-dimensional pad at a predetermined pressure; and separating the three-dimensional pad from the edge area with the plurality of conductive ribbons remaining in the edge area. 20. The manufacturing method as claimed in claim 11 , wherein the forming the plurality of side wirings comprises: applying, by a nozzle, a conductive ink on the glass substrate from a connection pad of the plurality of connection pads to the edge area; rotating the glass substrate relative to the nozzle; and applying, by the nozzle, the conductive ink on the glass substrate from the chamfered surface toward a side surface the glass substrate.

Assignees

Inventors

Classifications

  • H10W90/00Primary

    Package configurations · CPC title

  • of conductive parts of the interconnections · CPC title

  • of interconnections · CPC title

  • Interconnections (of active-matrix LED displays H10H29/49) · CPC title

  • Interconnections, e.g. wiring lines or terminals (connection of the pixel electrodes to the driving transistors H10H29/39) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11056630B2 cover?
A display module includes a glass substrate having a front surface and a back surface opposite to the front surface; a TFT layer; LEDs mounted on the TFT layer; and a plurality of side wirings formed at intervals in an edge area of the glass substrate, and the edge area includes a first area corresponding to a side surface of the glass substrate, a second area adjacent to the side surface, and …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).