Method of forming a metal silicide transparent conductive electrode

US11056610B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11056610-B2
Application numberUS-201816053959-A
CountryUS
Kind codeB2
Filing dateAug 3, 2018
Priority dateDec 7, 2011
Publication dateJul 6, 2021
Grant dateJul 6, 2021

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: providing a substrate; and forming, on said substrate, a metal silicide nanowire network for a transparent conducting film such that said metal silicide nanowire network comprises multiple metal silicide nanowires fused together in a grid on said substrate by forming a metal layer on said substrate; printing a first set of multiple parallel silicon nanowires on said metal layer; subsequently printing a second set of multiple parallel silicon nanowires on said metal layer over said first set of multiple parallel silicon nanowires such that silicon nanowires in said second set of multiple parallel silicon nanowires are perpendicular to silicon nanowires in said first set of multiple parallel silicon nanowires; performing a silicidation anneal to cause metal atoms from said metal layer to react with silicon material in said first set of multiple parallel silicon nanowires and said second set of multiple parallel silicon nanowires thus forming a plurality of metal silicide nanowires; and fusing said plurality of metal silicide nanowires into said grid on said substrate. 2. A method, comprising: forming, on a substrate, a metal silicide nanowire network for a transparent conducting film such that said metal silicide nanowire network comprises multiple metal silicide nanowires fused together in a grid on said substrate by printing a first set of multiple parallel silicon nanowires on said substrate; subsequently printing a second set of multiple parallel silicon nanowires on said substrate over said first set of multiple parallel silicon nanowires such that silicon nanowires in said second set of multiple parallel silicon nanowires are perpendicular to silicon nanowires in said first set of multiple parallel silicon nanowires; forming a metal layer over said first set of multiple parallel silicon nanowires and said second set of multiple parallel silicon nanowires; performing a silicidation anneal to cause metal atoms from said metal layer to react with silicon material in said first set of multiple parallel silicon nanowires and said second set of multiple parallel silicon nanowires thus forming a plurality of metal silicide nanowires; and fusing said plurality of metal silicide nanowires into said grid on said substrate. 3. A method, comprising: forming, on a substrate, a metal silicide nanowire network for a transparent conducting film such that said metal silicide nanowire network comprises multiple metal silicide nanowires fused together in a grid on said substrate by printing a first set of multiple parallel metal nanowires on said substrate; subsequently printing a second set of multiple parallel metal nanowires on said substrate over said first set of multiple parallel metal nanowires such that metal nanowires in said second set of multiple parallel metal nanowires are perpendicular to metal nanowires in said first set of multiple parallel metal nanowires; forming a silicon layer over said first set of multiple parallel metal nanowires and said second set of multiple parallel metal nanowires; performing a silicidation anneal to cause metal atoms from said metal nanowires in said first set of multiple parallel silicon nanowires and said second set of multiple parallel silicon nanowires react with silicon material in said silicon layer thus forming a plurality of metal silicide nanowires; and fusing said plurality of metal silicide nanowires into said grid on said substrate. 4. The method according to claim 1 , further comprising: coating said metal silicide nanowire network with a transparent polymer layer so as to fill gaps within said metal silicide nanowire network. 5. The method according to claim 4 , said transparent polymer layer comprising a polymer layer containing conductive particles or a conductive polymer layer. 6. The method according to claim 1 , further comprising: transferring said metal silicide nanowire network from said substrate to another substrate. 7. The method according to claim 1 , wherein said multiple metal silicide nanowires comprise any of nickel (Ni) silicide nanowires, cobalt (Co) silicide nanowires, tungsten (W) silicide nanowires, chromium (Cr) silicide nanowires, platinum (Pt) silicide nanowires, titanium (Ti) silicide nanowires, molybdenum (Mo) silicide nanowires, and palladium (Pd) silicide nanowires. 8. The method according to claim 2 , further comprising: coating said metal silicide nanowire network with a transparent polymer layer so as to fill gaps within said metal silicide nanowire network. 9. The method according to claim 8 , said transparent polymer layer comprising a polymer layer containing conductive particles or a conductive polymer layer. 10. The method according to claim 2 , further comprising: transferring said metal silicide nanowire network from said substrate to another substrate. 11. The method according to claim 2 , wherein said multiple metal silicide nanowires comprise any of nickel (Ni) silicide nanowires, cobalt (Co) silicide nanowires, tungsten (W) silicide nanowires, chromium (Cr) silicide nanowires, platinum (Pt) silicide nanowires, titanium (Ti) silicide nanowires, molybdenum (Mo) silicide nanowires, and palladium (Pd) silicide nanowires. 12. The method according to claim 3 , further comprising: coating said metal silicide nanowire network with a transparent polymer layer so as to fill gaps within said metal silicide nanowire network. 13. The method according to claim 12 , said transparent polymer layer comprising a polymer layer containing conductive particles or a conductive polymer layer. 14. The method according to claim 13 , further comprising: transferring said metal silicide nanowire network from said substrate to another substrate. 15. The method according to claim 3 , wherein said multiple metal silicide nanowires comprise any of nickel (Ni) silicide nanowires, cobalt (Co) silicide nanowires, tungsten (W) silicide nanowires, chromium (Cr) silicide nanowires, platinum (Pt) silicide nanowires, titanium (Ti) silicide nanowires, molybdenum (Mo) silicide nanowires, and palladium (Pd) silicide nanowires.

Assignees

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Classifications

  • Transparent materials · CPC title

  • Manufacture or treatment · CPC title

  • made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers · CPC title

  • for photovoltaic cells · CPC title

  • for devices having potential barriers · CPC title

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What does patent US11056610B2 cover?
A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel sil…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10F71/138. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).