One selector one resistor MRAM crosspoint memory array fabrication methods

Patent metadata

Field	Value
Publication number	US-11056534-B2
Application number	US-201916460820-A
Country	US
Kind code	B2
Filing date	Jul 2, 2019
Priority date	Jun 27, 2019
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.

First claim

The invention claimed is:

1. A memory array comprising:
a first memory level comprising:
a plurality of memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element;
a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells;
a plurality of word lines and a plurality of bit lines, wherein each memory cell is disposed between one of the plurality of word lines and one of the plurality of bit lines,

wherein the plurality of memory cells comprise:
a first memory cell disposed below a corresponding one of the vias; and
a second memory cell disposed above a corresponding one of the vias.

2. The memory array of claim 1 , wherein each memory cell is disposed above or below a corresponding one of the vias.

3. The memory array of claim 1 , wherein the plurality of memory cells comprises a first layer of memory cells and a second layer of memory cells disposed above the first layer of memory cells.

4. The memory array of claim 1 , wherein each selector element comprises one or more of a threshold selector device, a conductive bridge threshold selector device, an ovonic threshold switch, and a Metal Insulator Transition of a Phase Transition Material type threshold selector device.

5. The memory array of claim 1 , wherein each selector element comprises one or more of SiTe, CTe, BTe, AlTe, SiAsTe, GeAsSe, GeAsSeSi, V 0 2 , and NbO 2 .

6. The memory array of claim 1 , wherein each selector element comprises HfOx doped with one or more of Cu, Ag, or similar metallic ion.

7. The memory array of claim 1 , wherein each memory cell is vertically-oriented.

8. The memory array of claim 1 , comprising a cross-point memory array.

9. The memory array of claim 1 , further comprising a second memory level disposed above the first memory level.

10. The memory array of claim 9 , wherein the first memory level and the second memory level share one of the plurality of word lines and the plurality of bit lines.

11. A method of forming a memory array, the method comprising:
forming a plurality of first memory cell pillars, each first memory cell pillar comprising a corresponding first magnetic material layer structure and a corresponding first selector element;
forming a first dielectric material layer around each first memory cell pillar;
forming first interstices between adjacent first memory cell pillars;
forming first vias in the first interstices;
forming a plurality of second memory cell pillars, each second memory cell pillar comprising a corresponding second magnetic material layer structure and a corresponding second selector element;
forming a second dielectric material layer around each second memory cell pillar;
forming second interstices between adjacent second memory cell pillars; and
forming second vias in the second interstices,
wherein each second memory cell pillar is disposed over a corresponding one of the first vias, and each first memory cell pillar is disposed under a corresponding one of the second vias.

12. The method of claim 11 , wherein the first selector elements comprise one or more of SiTe, CTe, BTe, AlTe, SiAsTe, GeAsSe, GeAsSeSi, VO 2 , and NbO 2 .

13. The method of claim 11 , wherein the first selector elements comprise a volatile conductive bridge type of selector with HfOx doped with one or more of Cu, Ag, or similar ions.

14. The method of claim 11 , wherein each first memory cell pillar is vertically-oriented.

15. The method of claim 11 , wherein each second memory cell pillar is vertically-oriented.

16. The method of claim 11 , wherein the memory array comprises a cross-point memory array.

Assignees

• Sandisk Technologies Llc

Inventors

• Wan Lei
• Wu Tsai-Wei
• Katine Jordan A

Classifications

• H10N52/85

  Materials of the active region · CPC title

• H10N52/01

  Manufacture or treatment · CPC title

• H10B63/20

  comprising selection components having two electrodes, e.g. diodes · CPC title

• H10B61/10 Primary

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title