Method of fabricating a monolithic sensor device from a layered structure

Patent metadata

Field	Value
Publication number	US-11056531-B2
Application number	US-201816619444-A
Country	US
Kind code	B2
Filing date	Jun 1, 2018
Priority date	Jun 6, 2017
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A method of fabricating a field-effect transistor in which a native oxide layer is removed prior to etching a gate recess. The cleaning step ensures that the etch of the gate recess starts at the same time across an entire sample, such that a uniform gate recess depth and profile can be achieved across an array of field-effect transistors. This results in a highly uniform switch-off voltage for the field-effect transistors in the array.

First claim

The invention claimed is:

1. A method of fabricating a monolithic sensor unit comprising a sensor and field-effect transistor formed within a layered semiconductor stack, the layered semiconductor stack having a substrate, a first semiconductor device layer for forming the field-effect transistor deposited on the substrate and a second semiconductor device layer deposited on the first semiconductor device layer, the second semiconductor device layer providing an active region for the sensor, wherein the method comprises the steps of:
selectively etching a portion of the second semiconductor device layer to expose a surface of the first semiconductor device layer; and
performing a wet etch process on a portion of the first semiconductor device layer to form a gate recess in the first semiconductor device layer, wherein the wet etch process comprises:
applying a native oxide removal solution to remove native oxide from the exposed surface of the first semiconductor device layer, and
applying an etchant solution to remove material from the first semiconductor device layer and thereby form the gate recess.

2. The method according to claim 1 , wherein the step of applying the etchant solution occurs immediately after the step of applying the native oxide removal solution.

3. The method according to claim 1 , wherein the wet etch process further comprises applying a surface active agent solution to the exposed surface of the first semiconductor device layer.

4. The method according to claim 3 , wherein the step of applying the surface active agent solution occurs immediately before the step of applying the native oxide removal solution.

5. The method according to claim 1 , wherein the native oxide removal solution further comprises a surface active agent.

6. The method according to claim 1 , wherein the wet etch process is performed repeatedly to obtain a gate recess having a predetermined depth.

7. The method according to claim 6 further comprising the step of detecting a depth of the gate recess during the step of performing the wet etch process.

8. The method according to claim 1 , wherein the layered semiconductor stack further comprises a buffer layer between the first semiconductor device layer and the second semiconductor device layer.

9. The method according to claim 1 , wherein the sensor is a photodiode sensitive to radiation in the mid-infrared region.

10. The method according to claim 9 , wherein the active region of the second semiconductor device layer comprises InSb.

11. The method according to claim 10 , wherein the layered semiconductor stack comprises a GaSb buffer layer between the first semiconductor device layer and the second semiconductor device layer, and
wherein the step of selectively etching a portion of the second semiconductor device layer further comprises applying a buffer etchant solution for removing the GaSb buffer layer to expose the surface of the first semiconductor device layer.

12. The method according to claim 11 , wherein the buffer etchant solution comprises tetramethylammonium hydroxide.

13. The method according to claim 1 , wherein the first semiconductor device layer comprises a GaAs channel layer for the field-effect transistor.

14. The method according to claim 1 further comprising depositing a gate electrode in the gate recess to form a gate electrode of the field-effect transistor.

15. The method according to claim 14 further comprising, before depositing the gate electrode in the gate recess, depositing an insulating layer in the gate recess.

16. The method according to claim 1 further comprising depositing a source electrode and a drain electrode on the surface of the first semiconductor device layer to form a source electrode and drain electrode of the field-effect transistor, respectively.

17. The method according to claim 16 , wherein the second semiconductor device layer is a multilayer comprising:
a first contact layer having a first sensor electrode thereon,
an active layer deposited on the first contact layer, and
a second contact layer deposited on the active layer and having a second sensor electrode thereon, and wherein the method further comprising the steps of:
depositing a planarising section to form a ramp between the first sensor electrode and the drain electrode; and
depositing an interconnection on the planarising section to electrically connect the first sensor electrode to the drain electrode.

18. The method according to claim 1 wherein the layered semiconductor stack comprises a common contact layer for the first semiconductor device layer and the second semiconductor device layer, and wherein the method comprises:
depositing a first contact electrode on the surface of the first semiconductor device layer; and
depositing a second contact electrode on a surface of the second semiconductor device layer;
wherein the first contact electrode and the second contact electrode are arranged such that a current between the first contact electrode and the second contact electrode is controllable based on a bias voltage applied to the gate electrode.

19. The method according to claim 1 applied simultaneously at a plurality of locations on a common substrate to form an array of sensor units.

20. A monolithic sensor unit having a sensor integrated with a field-effect transistor, the sensor unit having a layered semiconductor stack comprising:
a substrate;
a first semiconductor device layer forming the field-effect transistor deposited on the substrate;
a second semiconductor device layer deposited on the first semiconductor device layer, the second semiconductor device layer providing an active region for the sensor;
a common contact layer disposed between the first semiconductor device layer and the second semiconductor device layer;
a first contact electrode deposited on a surface of the first semiconductor device layer;
a second contact electrode deposited on a surface of the second semiconductor device layer; and
a gate electrode for the field-effect transistor disposed in a gate recess formed in the first semiconductor device layer,
wherein the field-effect transistor is arranged to control, based on a bias voltage applied to the gate electrode, a current flowing between the first contact electrode and the second contact electrode.

21. The monolithic sensor unit according to claim 20 , wherein the layered semiconductor stack comprises a buffer layer for relaxing strain arising from a lattice mismatch between the first semiconductor device layer and the second semiconductor device layer.

22. The monolithic sensor unit according to claim 21 , wherein the sensor is a photodiode, and wherein the buffer layer enables charge carrier multiplication in the photodiode.

23. The monolithic sensor unit according to claim 21 , wherein the photodiode comprises an absorption region comprises InSb, and wherein the buffer layer comprises GaSb.

24. The monolithic sensor unit according to claim 20 , wherein the first semiconductor device layer comprises a GaAs channel layer for the field-effect transistor.

25. A focal plane array comprising a plurality of monolithic sensor units according to claim 20 formed on a common substrate.

Assignees

• Univ Glasgow Court

Inventors

• Cumming David Robert Sime
• Xie Chengzhi
• Pusino Vincenzo

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10F77/124

  comprising only Group III-V materials, e.g. GaAs · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/184

  Infrared image sensors · CPC title

• H10F39/014

  of CMOS image sensors · CPC title